• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.1
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• pp.93-102
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• 1994

This paper, presents SECRET(SEC REliability Tool), which predicts reliability problems related to the hot-carrier and electromigration effects on the submicron MOSFETs and interconnections. To simulate DC and AC lifetime for hot-carrier damaged devices, we have developed an accurate substrate current model with the geometric sensitivity, which has been verified over the wide ranges of transistor geometries. A guideline can be provided to design hot-carrier resistant circuits by the analysis of HOREL(HOT-carrier RFsistant Logic) effect, and circuit degradation with respect to physical parameter degradation such as the threshold voltage and the mobility can also be expected. In SECRET, DC and AC MTTF values of metal lines are calculated based on lossy transmission line analysis, and parasitic resistances, inductances and capacitances of metal lines are accurately considered when they operate in the condition of high speed. Also, circuit-level reliability simulation can be applied to the determination of metal line width and-that of optimal capacitor size in substrate bias generation circuit. Experimental results obtained from the several real circuits show that SECERT is very useful to estimate and analyze reliability problems.

• Proceedings of the KIPE Conference
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• 2002.07a
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• pp.480-484
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• 2002

A new active lossless snubber for half-bridge dual converter(that is called 'dual converter') is proposed in this paper. It features soft switching(ZVS) as well as turn-off snubbing in both main and auxiliary switches. As it uses parasitic components, such as leakage inductances and switch output capacitances etc, it helps the dual converter to operate at the higher frequency with a higher efficiency and smaller size reactive components. The operational principle, theoretical analysis, and design consideration are presented. To confirm the operation, features and validity of the proposed circuit, simulated results from an 1kW, 24V/DC-250V/DC are presented.

• Proceedings of the KIEE Conference
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• 1998.07f
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• pp.1876-1878
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• 1998

For an analysis and simulation of the conducted EMI of switching converters, an accurate simulation model for MOSFET is needed. This paper presents a new modeling approach, which incorporates DC output characteristics and AC dynamics especially the parasitic capacitances. It uses Pspice ABM(Analog Behavioral Model) and the MOSFET parameters can be obtained from the Data sheet in the frequency range of interest for EMI analysis. The model verified with an experimental setup and the EMI for a test converter is analyzed with respect to the MOSFET switching waveforms.

• Journal of the Korean Institute of Telematics and Electronics
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• v.18 no.2
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• pp.14-21
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• 1981

This paper describes a method for realizing RC active filters, by the use of the CGIC's In realizing the CGIC circuit, every element in the circuit is selected so as to minimize the effect of the non -ideal characteristic of operational amplifers, and an extra element is added to the, CGIC circuit to compensate the parasitic capacitances of the circuit. The CGIC s are utilized in the design of active filters using ladder embedding technique. The design procedure is presented in detail and the application is illustrated by the design of a band-pass filter of high order.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.54 no.9
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• pp.444-449
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• 2005

This paper proposes the new soft switching DC-DC converter. We reported the experimental results of the new soft switching DC-DC converter. The proposed converter is to resonate between the leakage inductance of the transformer and the parasitic capacitances of the main switches for zero voltage switching. The voltage stresses of the two switches are the input voltage, it can improve the efficiency and a reduced height used two transformers. Theoretical analysis of the converter along with experimental results is provided. Finally, a 3.3V/20A prototype converter operation at 100kHz is built and experimental waveform verifies the analysis.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.61 no.9
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• pp.1300-1305
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• 2012

A triaxial Blumlein pulse forming line has been designed to generate a pulse whose voltage is ~300 kV, pulse duration is ~5 ns, and rise time is ~500 ps. It turns out, however, that the rise time of the pulse becomes much longer than 500 ps due to parasitic inductances and capacitances existing inside the system. A peaking switch has been developed to shorten the rise time of the pulse from Blumlein pulse forming line. In the peaking switch, a wedge-shaped dielectric material (MC 901 nylon) is employed to surround the electrode on the antenna side. This shape inhibits an abrupt change of the output impedance, thereby minimizing the reflection of the output pulse. Experimental results show that the peaking switch is capable of improving the rise time of the pulse at a level of 500 ps.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.6
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• pp.981-987
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• 1986

This paper describes the CIREX(CIRcuit EXtractor), an automated CMOS circuit extraction program which provides SPICE2 input file by computing circuit connectivity and transistor dimensions from the CIF file. The CIREX also computes parasitic capacitance and resistance which makes it a valuable tool for timing analysis and detailed circuit simulation. A lattice model is used to calculate the interconnection resistances and substrate capacitances which can be replaced, as an option, by a node model for the worst case timing analysis of the circuit.

• ETRI Journal
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• v.27 no.3
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• pp.304-311
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• 2005

We report on the fabrication of an AlGaAs/InGaAs/GaAs pseudomorphic high electron mobility transistor (PHEMT) using a dielectric-defined process. This process was utilized to fabricate $0.12\;{\mu}m\;{\times}\;100 {\mu}m$ T-gate PHEMTs. A two-step etch process was performed to define the gate footprint in the $SiN_x$. The $SiN_x$ was etched either by dry etching alone or using a combination of wet and dry etching. The gate recessing was done in three steps: a wet etching for removal of the damaged surface layer, a dry etching for the narrow recess, and wet etching. A structure for the top of the T-gate consisting of a wide head part and a narrow lower layer part has been employed, taking advantage of the large cross-sectional area of the gate and its mechanically stable structure. From s-parameter data of up to 50 GHz, an extrapolated cut-off frequency of as high as 104 GHz was obtained. When comparing sample C (combination of wet and dry etching for the $SiN_x$) with sample A (dry etching for the $SiN_x$), we observed an 62.5% increase of the cut-off frequency. This is believed to be due to considerable decreases of the gate-source and gate-drain capacitances. This improvement in RF performance can be understood in terms of the decrease in parasitic capacitances, which is due to the use of the dielectric and the gate recess etching method.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.10 no.2
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• pp.269-273
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• 2009

A voltage regulator can be used to reduce the effect of the power-supply noise on the control voltage of the VCO. An accurate analysis of the voltage regulator circuit is needed for the optimal design of the voltage regulator. This paper clarifies an inaccuracy in a recent paper on the replica-compensated regulator far supply-regulated PLLs: neglect of MOSFET parasitic capacitances. As a consequence, an improved analytical model is derived for the replica-compensated voltage regulator. The derived model is verified through circuit simulation. The voltage regulator has been fabricated in a standard $0.18{\mu}m$ 1P6M CMOS technology. The chip area is $1mm^2$.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.4
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• pp.484-492
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• 2015

This paper proposes a PWM phase-shift circuit to make that the LED lighting system distributes the channel currents evenly for any number of LED strings by generating evenly phase-shifted PWM signals for multiple LED driver ICs. The evenly distributed channel currents reduce the peak current, the decoupling capacitor size, and EMI noise. The PWM phase-shift circuit makes an arbitrary degree of PWM phase-shift by using a resistor and a capacitor. It measures the RC delay once. It reduces the number of external resistors and capacitors by providing zero and 180 degree phase-shift modes requiring no resistor and capacitor. An LED driver IC with the PWM phase-shift circuit was fabricated with a $0.35{\mu}m$ BCDMOS process. The PWM phase-shift circuit receives a PWM signal of 50 Hz~20 kHz at $f_{CLK}=450kHz$ and it generates a $0{\sim}360^{\circ}$ phase-shifted PWM signal with $R=0{\sim}1.1M{\Omega}$ at C=1 nF and $f_{PWM}=1kHz$. The measured phase errors are 1.74~3.94% due to parasitic capacitances.