• JSTS:Journal of Semiconductor Technology and Science
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• 제4권1호
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• pp.52-62
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• 2004

In this paper we look at the effect of Fringe-Enhanced-Barrier-lowering (FEBL) for high-K dielectric MOSFETs and the dependence of FEBL on various technological parameters (spacer dielectrics, overlap length, dielectric stack, S/D junction depth and dielectric thickness). We show that FEBL needs to be contained in order to maintain the performance advantage with scaled high-K dielectric MOSFETs. The degradation in high-K dielectric MOSFETs is also identified as due to the additional coupling between the drain-to-source that occurs through the gate insulator, when the gate dielectric constant is significantly higher than the silicon dielectric constant. The technology parameters required to minimize the coupling through the high-K dielectric are identified. It is also shown that gate dielectric stack with a low-K material as bottom layer (very thin $SiO_2$ or oxy-nitride) will be helpful in minimizing FEBL. The circuit performance issues with high-K MOS transistors are also analyzed in this paper. An optimum range of values for the dielectric constant has been identified from the delay and the energy dissipation point of view. The dependence of the optimum K for different technology generations has been discussed. Circuit models for the parasitic capacitances in high-K transistors, by incorporating the fringing effects, have been presented.

• Journal of Power Electronics
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• 제18권3호
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• pp.892-901
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• 2018

SiC MOSFETs have been used to improve system efficiency in high frequency converters due to their extremely high switching speed. However, this can result in undesirable parasitic oscillations in practical systems. In this paper, models of the key components are introduced first. Then, theoretical formulas are derived to calculate the switching oscillation frequencies after full turn-on and turn-off in clamped inductive circuits. Analysis indicates that the turn-on oscillation frequency depends on the power loop parasitic inductance and parasitic capacitances of the freewheeling diode and load inductor. On the other hand, the turn-off oscillation frequency is found to be determined by the output parasitic capacitance of the SiC MOSFET and power loop parasitic inductance. Moreover, the shifting regularity of the turn-off maximum peak voltage with a varying switching speed is investigated on the basis of time domain simulation. The distortion of the turn-on current is theoretically analyzed. Finally, experimental results verifying the above calculations and analyses are presented.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권5호
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• pp.525-536
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• 2014

Recently, the first generation of mass production of FinFET-based microprocessors has begun, and scaling of FinFET transistors is ongoing. Traditional capacitance and resistance models cannot be applied to nonplanar-gate transistors like FinFETs. Although scaling of nanoscale FinFETs may alleviate electrostatic limitations, parasitic capacitances and resistances increase owing to the increasing proximity of the source/drain (S/D) region and metal contact. In this paper, we develop analytical models of parasitic components of FinFETs that employ the raised source/drain structure and metal contact. The accuracy of the proposed model is verified with the results of a 3-D field solver, Raphael. We also investigate the effects of layout changes on the parasitic components and the current-gain cutoff frequency ($f_T$). The optimal FinFET layout design for RF performance is predicted using the proposed analytical models. The proposed analytical model can be implemented as a compact model for accurate circuit simulations.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1999년도 추계학술대회 논문집
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• pp.557-560
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• 1999

The design of large area thin film transistor liquid crystal displays (TFT-LCDs) requires consideration of cross-talks between the data lines and pixel electrodes. These limits are imposed by the parasitic capacitive elements present in a pixel. The capacitive coupling of the data line signal onto the pixel causes a pixel voltage error. In this study semi-empirical capacitance model which is adopted from VLSI interconnection capacitance calculations was used to calculate mutual coupling capacitances. With calculated mutual coupling capacitances and given image pattern, the root mean square(RMS) voltage of pixel is calculated to see vertical cross-talk from the first to the last column. The information obtained from this study could be utilized to design the larger area and finer image quality panel.

• Journal of information and communication convergence engineering
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• 제6권1호
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• pp.43-46
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• 2008

This paper proposes an advanced test circuit for detecting the connectivity between a drum ring of laser printer and PCB. The detection circuit of charge sharing is proposed, which minimizes the influences of internal parasitic capacitances. The test circuit is composed of precharge circuit, analog comparator, level shifter. Its functional operation is verified using $0.6{\mu}m$ 3.3V/40V CMOS process parameter by HSPICE. Access time is100ns. Layout of the drum contact test circuit is $465{\mu}m\;{\times}\;117{\mu}m$.

• 대한전자공학회논문지
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• 제27권9호
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• pp.1378-1385
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• 1990

In this paper we propose a model which can predict well the logical errors come from the charge redistribution in domino gates. In this model the effect of the intrinsic capacitance between gate and channel of MOSFET's is considered. This effect is more important than the parasitic capacitance effect. The error by the proposed model is only 8% of that by the currently used model. This model can be used as a guide-line in the design of domino circuits.

• 전기학회논문지
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• 제56권4호
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• pp.683-692
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• 2007

An inverter driven induction motor has more superior dynamic characteristic than sine wave driven induction motor. But it has a problem with shaft voltage and bearing current in drive-motor system. This paper presents the analysis of bearing current in inverter-fed induction motor. The proposed method is based on using numerical method (FEM) to derive parasitic parameters in motor. Using the electric field analysis with FEM, the stored energy in dielectric materials of the motor can be calculated and the parasitic capacitances are obtained. Then we compared the proposed method with a conventional method in variable frequency and load conditions. From the comparision of simulation and experiment result, we confirmed that the proposed method is valid.

• ETRI Journal
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• 제31권6호
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• pp.741-748
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• 2009

We present an analysis of microstrip coupled lines (MCLs) used to improve the stability of a 60 GHz narrowband amplifier. The circuit has a 4-stage structure implementing MCLs instead of metal-insulator-metal (MIM) capacitors for the unconditional stability of the amplifier and yield enhancement. The stability parameter, U, is used to compare the stability of MCLs with that of MIM capacitors. Experimental results show that MCLs are more stable than MIM capacitors with the same capacitances as MCLs because the parasitic parallel resistances of MCLs are lower than those of MIM capacitors. Moreover, the bandwidth of an amplifier using MCLs is narrower than one using MIM capacitors because the parasitic series inductances of MCLs are higher than those of MIM capacitors.

• Journal of Power Electronics
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• 제5권4호
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• pp.247-256
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• 2005

In order to harvest power in an efficient manner from a micro piezoelectric (PZT) device for charging the battery of a remote system, a new AC/DC resonant pulse power converter is proposed. The proposed power converter has two stages in the power conversion process. The first stage includes N-type MOSFET full bridge rectifier. The second stage includes a boost converter having an N-type MOSFET and a P-type MOSFET. MOSFETs work in the $1^{st}$ or $3^{rd}$ quadrant region. A small inductor for the boost converter is assigned in order to make the size of the power converter as small as possible, which makes the on-interval of the MOSFET switch of the boost converter ultimately short. Due to this short on-interval, the parasitic junction capacitances of MOSFETs affect the performance of the power converter system. In this paper, the performance of the new converter is analytically and experimentally evaluated with consideration of the parasitic capacitance of switching devices.

• 한국전자파학회논문지
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• 제11권6호
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• pp.876-885
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• 2000

추가적인 DC 측정이나 반복 계산법 또는 최적화 방법에 의존하지 않고도, 정상적인 바이어스(Normal activebias) 조건에서 측정하 S-파라미터로부터 MESFET과 HEMT의 외부 기생 저항을 간단히 구할 수 있는 방법이 제시되었다. 이를 위해서 zero 바이어스 조건에서 측정한 Z-파라미터로부터 Rs와 Rd의 차이를 구할수 있다는 사실이 이용된다. 측정한 S-파라미터로부터 외부 기생 인덕터와 캐패시터의 효과를 제거하면, 내부 소자와 외부 기생 저항을 포함한 새로운 소자를 정의할 수 있다. 내부 소자의 Y-파라미터인 Yint,11과 Yint,12의 실수부 값이 이론적으로 0이라는 사실을 이용하여 S-, Y-, Z-파라미터 행렬간의 상화관계를 이용하여 기생 저항 값을 쉽게계산할수 있다. 제시된 방법으로 기생 저항들을 구하고, 이 결과를 이용하여 내부 소자 등가회로를 구한 후에 40GHz까지 S-파라미터를 계산한 결과, 측정된 S-파라미터와 잘 일치하였다.