• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 ITC-CSCC -1
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• pp.289-293
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• 2000

We propose two new algorithms for parallelism-independent scheduling. The machine code generated from the compiler using these algorithms in its scheduling phase is parallelism-independent code, executable in minimum time regardless of the number of the processors in the parallel computer. Our new algorithms have the following phases: finding the minimum number of processors on which the program can be executed in minimal time, scheduling by an heuristic algorithm for this predefined number of processors, and serialization of the parallel schedule according to the earliest start time of the tasks. At run time tasks are taken from the serialized schedule and assigned to the processor which allows the earliest start time of the task. The order of the tasks decided at compile time is not changed at run time regardless of the number of the available processors which means there is no out-of-order issue and execution. The scheduling is done predominantly at compile time and dynamic scheduling is minimized and diminished to allocation of the tasks to the processors. We evaluate the proposed algorithms by comparing them in terms of schedule length to the CP/MISF algorithm. For performance evaluation we use both randomly generated DAGs (directed acyclic graphs) and DACs representing real applications. From practical point of view, the algorithms we propose can be successfully used for scheduling programs for in-order superscalar processors and shared memory multiprocessor systems. Superscalar processors with any number of functional units can execute the parallelism-independent code in minimum time without necessity for dynamic scheduling and out-of-order issue hardware. This means that the use of our algorithms will lead to reducing the complexity of the hardware of the processors and the run-time overhead related to the dynamic scheduling.

• 한국정보처리학회논문지
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• 제5권5호
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• pp.1172-1184
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• 1998

명령어 재배치는 ILP(Instruction Level Parallelism) 프로세서의 병렬성을 활용하는 주요한 코드 최적화 기법이다. 명령어 재배치 알고리즘을 루프(loop)에 적용하면서 서로 다른 반복(iteration) 사이의 동시 수행 가능한 명령어들이 인접한 위치로 모여지는 소프트웨어 파이프라인(software pipeline)된 루프가 얻어진다. 그러나 루프로부터 병렬성을 추출하는 소프트웨어 파이프라인 방법은 주로 명령어사이의 자료 종속성에 근거하여 스케줄링을 수행하므로 그 자체에 무한한 병렬성을 가지고 있는 벡터 루프의 경우 그 병렬성을 충분히 드러내지 못한다는 문제점을 안고 있다. 본 논문에서는 이러한 벡터루프에 대해 프로그램의 목적 코드 레벨에서 행해질 수 있는 새로운 벡터 스케줄링 방법을 제안한다. 벡터 스케줄링 방법은 프로그램의 목적 코드 레벨에서 루프의 구조나 반복 조건, 그리고 자료 종속성 등에 대한 전체적인 정보에 기반하여 스케줄링을 수행함으로써 소프트웨어 파이프라인 방법보다 프로그램의 수행속도를 향상시킬 수 있다. 본 논문에서는 벡터 스케줄링을 수행한 결과를 전통적인 소프트웨어 파이프라인 방법에 대해 생산된 병렬 루프의 결과와 수행속도 측면에서 비교한다.

• 전자공학회논문지A
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• 제33A권5호
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• pp.155-164
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• 1996

The architecture of a programmable video codec IC is described that employs multiple vector processors in a single chip. The vector processors operate in parallel and communicate with one another through on-chip shared memories. A single scalar control processor schedules each vector processor independently to achieve real-tiem video coding with special vector instructions. With programmable interconnection buses, the proposed architecture performs multi-processing of tasks and data in video coding. Therefore, it can provide good parallelism as well as good programmability. especially, it can operate multithread video coding, which processes several independent image sequences simultaneously. We explain its scheduling, multithred video coding, and vector processor architectures. We implemented a prototype video codec with a 0.8um CMOS cell-based technology for the multi-standard videophone. This codec can execute video encoding and decoding simultaneously for the QCIF image at a frame rate of 30Hz.