• Smart Media Journal
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• v.11 no.9
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• pp.39-46
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• 2022

The WK-recursive network proposed by Vecchia and Sanges[1] is widely used in the design and implementation of local area networks and parallel processing architectures. It provides a high degree of regularity and scalability, which conform well to a design and realization of distributed systems involving a large number of computing elements. In this paper, the routing of a message is investigated on the WK-recursive network, which is key to the performance of this network. We present an efficient shortest path algorithm on the WK-recursive network, which is simpler than Chen and Duh[2] in terms of design complexity.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.3 no.4
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• pp.274-279
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• 2002

ATM packet switching technologies for the purpose of the B-ISDN service are focused on high performance which represents good qualities on throughput, packet loss, and packet delay. ATM switch designs on a class of parallel interconnection network have been researched. But these are based on the self-routing function of it. It leads to conflict with each other, and to lose the packets. Therefore, this paper proposes the method based on Sort-Banyan network should be adopted for optimal routing algorithm. It is difficult to expect good hardware complexity. For good performance, a switch design based on the development of new routing algorithm is required. For the design of switch network, the packet distributor and multiplane are proposed. They prevent each packet from blocking as being transmitted selectively by two step distributed decision algorithm. This switch will be proved to be a good performance switch network that internal blocking caused from self-routing function is removed. Also, it is expected to minimize the packet loss and decrease the packet delay according to packet transmission.

• Journal of Korean Institute of Industrial Engineers
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• v.25 no.4
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• pp.490-499
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• 1999

Vehicle routing problem(VRP) is known to be NP-hard problem, and good heuristic algorithm needs to be developed. To develop a heuristic algorithm for the VRP, this study suggests a parallel genetic algorithm(PGA), which determines each vehicle route in order to minimize the transportation costs. The PGA developed in this study uses two dimensional array chromosomes, which rows represent each vehicle route. The PGA uses new genetic operators. New mutation operator is composed of internal and external operators. internal mutation swaps customer locations within a vehicle routing, and external mutation swaps customer locations between vehicles. Ten problems were solved using this algorithm and showed good results in a relatively short time.

• Journal of Communications and Networks
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• v.13 no.4
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• pp.408-417
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• 2011

The stringent performance requirement for the high efficiency of routing protocols on the Internet can be satisfied by exploiting the threaded border gateway protocol (TBGP) on multi-cores, but the state-of-the-art TBGP performance is restricted by a mass of contentions when racing to access the routing table. To this end, the highly-efficient parallel access approach appears to be a promising solution to achieve ultra-high route processing speed. This study proposes a general routing table structure consisting of two-level tries for fast parallel access, and it presents a heuristic-based divide-and-recombine algorithm to solve a mass of contentions, thereby accelerating the parallel route updates of multi-threading and boosting the TBGP performance. As a projected TBGP, this study also modifies the table operations such as insert and lookup, and validates their correctness according to the behaviors of the traditional routing table. Our evaluations on a dual quad-core Xeon server show that the parallel access contentions decrease sharply by 92.5% versus the traditional routing table, and the maximal update time of a thread is reduced by 56.8 % on average with little overhead. The convergence time of update messages are improved by 49.7%.

• Journal of Korea Multimedia Society
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• v.18 no.9
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• pp.1083-1090
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• 2015

A generalized recursive circulant network(GR) is widely used in the design and implementation of local area networks and parallel processing architectures. In this paper, we investigate the routing of a message on this network, that is a key to the performance of this network. We would like to transmit maximum number of packets from a source node to a destination node simultaneously along paths on this network, where the i^th packet traverses along the i^th path. In order for all packets to arrive at the destination node securely, the i^th path must be node-disjoint from all other paths. For construction of these paths, employing the Hamiltonian Circuit Latin Square(HCLS), a special class of (n x n) matrices, we present O(n²) parallel routing algorithm on generalized recursive circulant networks.

• Smart Media Journal
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• v.7 no.2
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• pp.9-14
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• 2018

The k-ary n-cube $Q^k_n$ is widely used in the design and implementation of parallel and distributed processing architectures. It consists of $k^n$ identical nodes, each node having degree 2n is connected through bidirectional, point-to-point communication channels to different neighbors. On $Q^k_n$ we would like to transmit packets from a source node to 2n destination nodes simultaneously along paths on this network, the $i^{th}$ packet will be transmitted along the $i^{th}$ path, where $0{\leq}i{\leq}2n-1$. In order for all packets to arrive at a destination node quickly and securely, we present an $O(n^3)$ routing algorithm on $Q^k_n$ for generating a set of one-to-many node-disjoint and nearly shortest paths, where each path is either shortest or nearly shortest and the total length of these paths is nearly minimum since the path is mainly determined by employing the Hungarian method.

• Journal of Korean Institute of Industrial Engineers
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• v.15 no.1
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• pp.23-30
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• 1989

The routing flexibility in FMSs can be achieved through two levels : the parallel operations and the alternative stations. To accommodate this pertaining flexibility for part routing in FMSs, a hierarchical routing principle is developed which considers both the routing flexibility and the performance effectiveness, which can also be easily implemented. For the proper implementation of this routing algorithm, the required information flow is identified which turns out to be very simple.

• International Journal of Naval Architecture and Ocean Engineering
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• v.12 no.1
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• pp.596-604
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• 2020

Previous studies on pipe auto-routing algorithms generally used such algorithms as A*, Dijkstra, Genetic Algorithm, Particle Swarm Optimization, and Ant Colony Optimization, to satisfy the relevant constraints of its own field and improve the output quality. On the other hand, this study aimed to significantly improve path-finding speed by applying the Jump Point Search (JPS) algorithm, which requires lower search cost than the abovementioned algorithms, for pipe routing. The existing JPS, however, is limited to two-dimensional spaces and can only find the shortest path. Thus, it requires several improvements to be applied to pipe routing. Pipe routing is performed in a three-dimensional space, and the path of piping must be parallel to the axis to minimize its interference with other facilities. In addition, the number of elbows must be reduced to the maximum from an economic perspective, and preferred spaces in the path must also be included. The existing JPS was improved for the pipe routing problem such that it can consider the above-mentioned problem. The fast path-finding speed of the proposed algorithm was verified by comparing it with the conventional A* algorithm in terms of resolution.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.4
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• pp.93-102
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• 1995

This paper introduces a general purpose Associative Processor(AP) which is very efficient for search-oriented applications. The proposed architecture consists of three main functional blocks: Content-Addressable Memory(CAM) arry, row logic, and control section. The proposed AP is a Single-Instruction, Multiple-Data(SIMD) device based on a CAM core and an array of high speed processors. As an application for the proposed hardware, we present a parallel algorithm to solve a global routing problem in the layout process utilizing the processing capabilities of a rudimentary logic and the selective matching and writing capability of CAMs, along with basic algorithms such a minimum(maximum) search, less(greater) than search and parallel arithmetic. We have focused on the simultaneous minimization of the desity of the channels and the wire length by sedking a less crowded channel with shorter wire distance. We present an efficient mapping technique of the problem into the CAM structure. Experimental results on difficult examples, on randomly generated data, and on benchmark problems from MCNC are included.

• Journal of the Korea Institute of Military Science and Technology
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• v.20 no.4
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• pp.566-578
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• 2017

For optimizing the operation plan when strike packages attack multiple targets, this article suggests a new mathematical model and a parallel hybrid genetic algorithm (PHGA) as a solution methodology. In the model, a package can assault multiple targets on a sortie and permitted the use of mixed munitions for a target. Furthermore, because the survival probability of a package depends on a flight route, it is formulated as a mixed integer programming which is synthesized the models for vehicle routing and weapon-target assignment. The hybrid strategy of the solution method (PHGA) is also implemented by the separation of functions of a GA and an exact solution method using ILOG CPLEX. The GA searches the flight routes of packages, and CPLEX assigns the munitions of a package to the targets on its way. The parallelism enhances the likelihood seeking the optimal solution via the collaboration among the HGAs.