• The Transactions of The Korean Institute of Electrical Engineers
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• v.67 no.2
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• pp.270-276
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• 2018

Apache Spark is one of the high performance in-memory computing frameworks for big-data processing. Recently, to improve the performance, general-purpose computing on graphics processing unit(GPGPU) is adapted to Apache Spark framework. Previous Spark-GPGPU frameworks focus on overcoming the difficulty of an implementation resulting from the difference between the computation environment of GPGPU and Spark framework. In this paper, we propose a Spark framework based on a heterogenous pipeline computing with OpenCL to further improve the performance. The proposed framework overlaps the Java-to-Native memory copies of CPU with CPU-GPU communications(DMA) and GPU kernel computations to hide the CPU idle time. Also, CPU-GPU communication buffers are implemented with switching dual buffers, which reduce the mapped memory region resulting in decreasing memory mapping overhead. Experimental results showed that the proposed Spark framework based on a heterogenous pipeline computing with OpenCL had up to 2.13 times faster than the previous Spark framework using OpenCL.

• Proceedings of the KIEE Conference
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• 2005.07d
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• pp.2729-2731
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• 2005

In present, most of metallic structures(gas pipeline, oil pipeline, water pipeline, etc) are running parallel with subway and power line in seoul. Moreover subway system and power line make a stray current due to electrical corrosion on metallic structures. The owner of metallic structures has a burden of responsibility for the protection of corrosion and the prevention against big accident such as gas explosion or soil pollution and so on. So, they have to measure and analyze the data about P/S(Pipe to Soil) potential due to stray current of subway system. In this paper, results of development about Real-time Wireless Remote Monitoring System for Stray Current of Subway System are presented.

• Proceedings of the KIEE Conference
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• 2005.07d
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• pp.2732-2734
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• 2005

In present, most of metallic structures(gas pipeline, oil pipeline, water pipeline, etc) are running parallel with subway and power line in seoul. Moreover subway system and power line make a stray current due to electrical corrosion on metallic structures. The owner of metallic structures has a burden of responsibility for the protection of corrosion and the prevention against big accident such as gas explosion or soil pollution and so on. So, they have to measure and analyze the data about P/S(Pipe to Soil) potential due to stray current of subway system. So, we have developed the Real-time Wireless Remote Monitoring System for Stray Current of Subway System. In this system, the permanent buried type reference electrode is necessary. In this paper, results of development about the permanent buried type reference electrode($Cu/CuSO_4$) are presented.

• Proceedings of the KIEE Conference
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• 2005.11a
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• pp.145-147
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• 2005

In present, most of metallic structures(gas pipeline, oil pipeline, water pipeline, etc) are running parallel with subway and power line in seoul. Moreover subway system and power line make a stray current due to electrical corrosion on metallic structures. The owner of metallic structures has a burden of responsibility for the protection of corrosion and the prevention against big accident such as gas explosion or soil pollution and so on. So, they have to measure and analyze the data about P/S(Pipe to Soil) potential due to stray current of subway system. So, we have developed the Real-time Wireless Remote Monitoring System for Stray Current of Subway System. In this system, the permanent buried type reference electrode is necessary. In this paper, results of development of buried type reference electrode using porous ceramic$({\alpha}-Al_{2}O_{3})$ are presented.

• Proceedings of the Korean Information Science Society Conference
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• 2005.11a
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• pp.826-828
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• 2005

인텔의 IA-64 프로세서는 명령어 수준의 병렬수행을 지원하는 EPIC (Explicitly Parallel Instruction Computing) 구조를 채택하고 있으며 컴파일러가 순차적 코드에서 병렬 수행이 가능한 독립적인 명령어들을 스케줄링 하도록 되어있다. 본 논문에서는 IA-64 스케줄링을 위해 향상된 파이프라인 스케줄링 (Enhanced Pipeline Scheduling, EPS) 기법[1]을 적용한 결과를 소개한다. EPS는 루프수준의 병렬화를 위한 소프트웨어 파이프라이닝 (software pipelining)기법으로 전역 스케줄링 (global Scheduling) 기법을 기반으로 하고 있다. 우리는 IA-64 프로세서를 위한 공개소스 컴파일러인 ORC (Open Research Compiler)에 EPS를 구현하고 실제 프로세서인 Itanium에서 실험을 수행하였다. 상용 프로세서와 컴파일러에 구현과 튜닝을 하는 과정에서 얻은 경험을 소개하고 기존의 ORC 컴파일러와 비교하여 얻은 성능 향상을 보고하고 분석한다.

• The Journal of Information Technology
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• v.10 no.3
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• pp.33-45
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• 2007

Systolic Array Processor is used for designing the special purpose processor in Digital Signal Processing, Computer Graphics, Neural Network Applications etc., since it has the characteristic of parallelism, pipeline processing and architecture of regularity. But, in case of using general design method, it has intial waiting period as large as No. of PE-1. And if the connected system needs parallel and simultaneous outputs, processor has some problems of the performance, since it generates only one output at each clock in output state. So in this paper, one dimensional Systolic Array Processor that is designed according to the dependance of data and operations using the partitioned sub-matrix is proposed for the purpose of improving the performance. 1-D Systolic Array using 4 partitioned sub-matrix has efficient method in case of considering those two problems.

• Proceedings of the KIEE Conference
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• 2002.07a
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• pp.154-155
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• 2002

The demand of the power and gas energy have been rapidly increasing with the industralization, therefore, the area where buried pipelines run parallel with the adjacent power lines and cross them increases in Seoul as well as other cities. These situation cause AC interference from the power lines. However, there aren't any standards to preserve the pipelines from AC interference in Korea. This study introduces the separation distance to protection of buried pipeline from arc strikes caused by power line ground fault current. And this study examines and compares the arc distance through case study.

• Proceedings of the KIEE Conference
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• 2005.10c
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• pp.282-284
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• 2005

When an underground pipeline runs parallel with DC traction systems, it suffers from DC traction interference. Because the train is fed by the substation through the overhead wire and return current back to the substation via the rails. If these return rails are poorly insulated from earth, DC current leak into the earth and can be picked up by nearby pipeline. It may bring about large-scale accidents even in cathodically protected systems. In this paper we analyze the influence on lead wire method of distributed ICCP(impressed current cathodic protection) systems for mitigation of DC traction interference using the simulation software CatPro.

• Proceedings of the KIEE Conference
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• 2005.07b
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• pp.1660-1662
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• 2005

When an underground pipeline runs parallel with DC traction systems, it suffers from DC traction interference. Because the train is fed by the substation through the overhead wire and return current back to the substation via the rails. If these return rails are poorly insulated from earth, DC current leak into the earth and can be picked up by nearby pipeline. It may bring about large-scale accidents even in cathodically protected systems. In this paper we analyze the anode location of distributed impressed current cathodic protection systems for the mitigation of DC traction interference on buried pipelines using the simulation software CatPro. We can get a fix on the anode location.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.1
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• pp.51-58
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• 2007

This paper presented an adaptive pipeline architecture for a high-performance and low-power asynchronous processor. The proposed pipeline architecture employed a stage-skipping and a stage-combining scheme. The stage-skipping scheme can skip the operation of a bubble stage that is not used pipeline stage in an instruction execution. In the stage-combining scheme, two consecutive stages can be joined to form one stage if the latter stage is empty. The proposed pipeline architecture could reduce the processing time and power consumption. The proposed architecture supports multi-processing in the EX stage that executes parallel 4 instructions. We designed an asynchronous microprocessor to estimate the efficiency of the proposed pipeline architecture that was synthesized to a gate level design using a $0.35-{\mu}m$ CMOS standard cell library. We evaluated the performance of the target processor using SPEC2000 benchmark programs. The proposed architecture showed about 2.3 times higher speed than the asynchronous counterpart, AMULET3i. As a result, the proposed pipeline schemes and architecture can be used for asynchronous high-speed processor design