• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.707-710
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• 2005

In this paper, we propose a new communication network for on-chip communication. The network is based on a direct sequence code division multiple access (DS-CDMA) technique. The new communication network is suitable for a parallel processing system and also drastically reduces the I/O pin count. Our network architecture is mainly divided into a CDMA-based network interface (CNI), a communication channel, a synchronizer. The network includes a reverse communication channel for reducing latency. The network decouples computation task from communication task by the CNI. An extreme truncation is considered to simplify the communication link. For the scalability of the network, we use a PN-code reuse method and a hierarchical structure. The network elements have a modular architecture. The communication network is done using fully synthesizable Verilog HDL to enhance the portability between process technologies.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.7
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• pp.1833-1841
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• 1996

Recently, by emerging of the ALE techniques that make it possible to providereliable communications link automatically, high frequency communiation is newly used as emergency communication and back-up for satellite communications. ALE signal is transmitted in burst, and the received signal is subject to distortions by detrimental multipath fading channels. In the case of that channel, the performance of ALE system is highly dependent upon that of synchronization techniques. In this paper, M-ary FSK signals are detected by a bank of bandpass filter, which is implemented using recusive DFT(Discrete Fourier Transform). Also an acquisition and trancking algorithm are designed uisng parallel structure and early-late-gate methods respectively. Finally, we verify the performance ofthe proposed synchronization algorithm by the computer simulation.

• Journal of Industrial Technology
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• v.18
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• pp.323-328
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• 1998

A current controlled VSI-PWM rectifier and inverter with capacitor dc link is regarded as one of the most promising structures for three-phase to three-phase to three-phase power conversion. This type of converter normally requires twelve switches for a rectifier and inverter composed of self turn-off switch such as a bi-polar transistor or IGBT with an anti-parallel diode. In this paper, a new three-phase to three-phase converter for ac motor drives is proposed. The proposed converter employs only eight switches and has the capability of delivering sinusoidal input currents with unity power factor and bidirectional power flow. This paper describes the feasibility and the operational limitations of the proposed structure. A mathematical model of the system is derived using generalized modulation theory and experimental results for steady state and dynamic behavior are presented to verify the developed model.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.50 no.1
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• pp.38-44
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• 2001

This paper investigates the direct adaptive control of nonlinear systems using RBFN(radial basis function networks). The structure of the controller consists of a fixed PD controller and a RBFN controller in parallel. An adaptation law for the parameters of RBFN is developed based on the Lyapunov stability theory to guarantee the stability of the overall control system. The filtered tracking error between the system output and the desired output is shown to be UUB(uniformly ultimately bounded). To evaluate the performance of the controller, the proposed method is applied to the trajectory contro of the two-link manipulator.

• Proceedings of the KIEE Conference
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• 1999.07g
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• pp.2992-2994
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• 1999

This paper investigates the direct adaptive control of nonlinear systems using RBFN(radial basis function networks). The structure of the controller consists of a fixed PD controller and a RBFN controller in parallel. An adaptation law for the weight adjustment is developed based on the Lyapunov stability theory to guarantee the stability of the overall control scheme. Also, the tracking errors between the system outputs and the desired outputs converge to zero asymptotically. To evaluate the performance of the controller, the proposed method is applied to the trajectory control of the two-link manipulator.

• The Journal of Korea Robotics Society
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• v.14 no.4
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• pp.264-269
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• 2019

This paper presents mechanical design and control of a bio-inspired legged robot. To achieve a fast legged running mechanism, a novel linkage leg structure is designed based on hind legs of domestic cats. The skeletomuscular system and parallel leg movement of a cat are analyzed and applied to determine the link parameters. The hierarchical control architecture is designed according to the biological data to generate and modulate desired gaits. The effectiveness of the leg mechanism design and control is verified experimentally. The legged robot runs at a speed of 46 km/h, which is comparatively higher speed than other existing legged robots.

• The Transactions of the Korean Institute of Power Electronics
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• v.16 no.6
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• pp.587-593
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• 2011

A new high power density and low cost Photovoltaic Power Conditioning System (PV PCS) with energy storage system is proposed. Its high power density and cost effectiveness can be achieved through the unification of the maximum power point tracker and battery charger/discharger. Despite of the reduced power stage, the proposed system can achieve the same performances of maximum power point tracking and battery charging/discharging as the conventional system. Moreover, the high voltage stress across the link-capacitor can be relieved through the series-connected link-capacitor with the battery. Therefore, a large number of series/parallel-connected link-capacitors can be reduced by 4-times. Especially, when the utility power failure happens, both photovoltaic and battery energies can be supplied to the load with only one power stage. Therefore, it features a simpler structure, less mass, lower cost, and fewer devices. Finally, to confirm the operation, validity, and features of the proposed system, theoretical analysis and experimental results from a single phase AC 220Vrms/1.5kW prototype are presented.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.2000-2003
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• 2003

In recent years, robots have been used widely in industrial field and have been expanded as a result of continuous research and development for high-speed and miniaturization. The goal of this paper is to design the serial manipulator through kinematic analysis and to control the position and orientation of end-effector with respect to time. In general, a structure of industrial robot consists of several links connected in series by various types of joints, typically revolute and prismatic joints. The movement of these joints is determined in inverse kinematic analysis. Compared to the complicated structure of parallel and hybrid robot, open loop system retains the characteristic that each link is independent and is controlled easily. AC servo motor is used to place the robot end-effector toward the accurate point with the desired speed and power while it is operated by position control algorithm. The robot end-effector should trace the given trajectory within the appropriate time. The trajectory of end-effector can be displayed on the monitor of general personal computer through Opengl program.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.11 s.102
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• pp.1075-1085
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• 2005

The purpose of this paper is to design the architecture for synchronization of MB-OFDM UWB system that is being processed the standardization for Alt-PHY of WPAN(Wireless Personal Area Network) at IEEE802.15.3a and to analyze the implementation loss due to 4 parallel synchronization architecture for design or link margin. First an overview of the MB-OFDM UWB system based on IEEE802.15.3a Alt-PHY standard is described. The effects of non-ideal transmission conditions of the MB-OFDM UWB system including carrier frequency offset and sampling clock offset are analyzed to design a full digital architecture for synchronization. The synchronization architecture using 4-parallel structure is then proposed to consider the VLSI implementation including algorithms for carrier frequency offset and sampling clock offset to minimize the effects of synchronization errors. The overall performance degradation due to the proposed synchronization architecture is simulated to be with maximum 3.08 dB of the ideal receiver in maximum carrier frequency offset and sampling clock offset tolerance fir MB-OFDM UWB system.

• Journal of KIISE:Computer Systems and Theory
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• v.27 no.6
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• pp.608-618
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• 2000

We consider the problem of placing resources in a distributed computing system so that certain performance requirements may be met while minimizing the number of required resource copies, irrespective of node or link failures. To meet the requirements for high performance and high availability, minimum number of resource copies should be placed in such a way that each node has at least two copies on the node or its neighbor nodes. This is called the fault-tolerant resource placement problem in this paper. The structure of a parallel or a distributed computing system is represented by a graph. The fault-tolerant placement problem is first transformed into the problem of finding the smallest fault-tolerant dominating set in a graph. The dominating set problem is known to be NP-complete. In this paper, searching for the smallest fault-tolerant dominating set is formulated as a state-space search problem, which is then solved optimally with the well-known A* algorithm. To speed up the search, we derive heuristic information by analyzing the properties of fault-tolerant dominating sets. Some experimental results on various regular and random graphs show that the search time can be reduced dramatically using the heuristic information.