• Journal of Satellite, Information and Communications
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• v.12 no.2
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• pp.61-64
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• 2017

A phase shifter is one of the key components that change the phase of an individual antenna in millimeter-wave phased array system. This paper presents a low-loss phase shifter design with two parallel 2-state amplifiers. To get the same gain of $0^{\circ}/180^{\circ}$ each state, delay lines are in the middle of each stage of the 2-Stage amplifiers. Normally, when adding AMPs in parallel, a power combiner/divider such as Wilkinson Power Combiner/Divider is added, but they are directly connected because it can cause added losses in silicon wafer. The measured data shows 12dB gain and 174-degree phase difference at 5GHz.

• ETRI Journal
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• v.36 no.1
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• pp.116-123
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• 2014

In this paper, a novel unequal broadband out-of-phase power divider (PD) is presented. Double-sided parallel-strip lines (DSPSLs) are employed to achieve an out-of-phase response. Also, an asymmetric dual-band matching structure with two external isolation resistors is utilized to obtain arbitrary unequal power division, in which the resistors are directly grounded for heat sinking. A through ground via (TGV), connecting the top and bottom sides of the DSPSLs, is used to short the isolation components. Additionally, this property can efficiently improve the broadband matching and isolation bandwidths. To investigate the proposed divider in detail, a set of design equations are derived based on the circuit theory and transmission line theory. The theoretical analysis shows that broadband responses can be obtained as proper frequency ratios are adopted. To verify the proposed concept, a sample divider with a power division of 2:1 is demonstrated. The measured results exhibit a broad bandwidth from 1.19 GHz to 2.19 GHz (59.2%) with a return loss better than 10 dB and port isolation of 18 dB.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.49 no.5
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• pp.15-20
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• 2012

In this paper, we show new method to find the error locations of received Reed-Solomon code word. New design is much faster and has much simpler logic circuit than the former design method. This optimization was possible by very simplified square/$X^4$ calculating circuit, parallel processing and not using the very complex Divider. The Reed Solomon decoder using this new Chien Machine can be applicated for data protection of almost all digital communication and consumer electronic devices.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.7 s.98
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• pp.681-689
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• 2005

This paper presents an ultra wide band(UWB) mixer using anti-parallel diode pair(APDP) with simulation and measurement results. The proposed mixer adopts the even-harmonic direct conversion mixing, which consists of a couple of filter, in-phase wilkinson power divider, wideband $45^{\circ}$ power divider, and APDP. The m mixer is operating over 3.1 to 4.8 GHz and producing quadrature(I/Q) outputs with a conversion loss of 18 dB and input third order intercept point($IIP_3$) of 15 dBm. I/Q outputs also have difference of about 0.5 dB and phase difference of ${\times}3^{\circ}$ and $P_{1dB}$ of 2 dBm.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.3
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• pp.33-42
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• 2003

This paper describes an efficient design of an asynchronous 16-bit divider using the NST (new Svoboda-Tung) algorithm. The divider is designed to reduce power consumption by using the asynchronous design scheme in which the division operation is performed only when it is requested. The divider consists of three blocks, i.e. pre-scale block, iteration step block, and on-the-fly converter block using asynchronous pipeline structure. The pre-scale block is designed using a new subtracter to have small area and high performance. The iteration step block consists of an asynchronous ring structure with 4 division steps for area reduction. In other to reduce hardware overhead, the part related to critical path is designed by a dual-rail circuit, and the other part is done by a single-rail circuit in the ring structure. The on-the-fly converter block is designed for high performance using the on-the-fly algorithm that enables parallel operation with iteration step block. The design results with 0.6${\mu}{\textrm}{m}$ CMOS process show that the divider consists of 12,956 transistors with 1,480 $\times$1,200${\mu}{\textrm}{m}$$^2$area and average-case delay is 41.7㎱.

• Journal of Advanced Navigation Technology
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• v.25 no.3
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• pp.229-235
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• 2021

This paper proposes a method of implementing an unequal power divider for high splitting ratios by using transmission lines connected with open and short stubs. The proposed method is an equivalent circuit analysis of a transmission line with an additional port so that it can be converted to an arbitrary impedance in the center of a 2-port transmission line and a 3-port transmission line with an open or short stub connected in parallel to each port. To prove the validity of this method, a Wilkinson power divider with k² = 20 dB splitting ratio and a Gysel power divider with k² = 17 dB splitting ratio were designed at a center frequency of 1 GHz using a 3-port transmission line equivalent circuit. The experimental results of the electrical characteristics are in good agreement with the simulation.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.3
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• pp.17-25
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• 1999

This paper proposes a new bit-serial multiplier/divider architecture to reduce the hardware complexity significantly and to maintain the same number of cycles compared with existing architectures. Since the proposed bit-serial multiplier/divider architecture does not extend the number of bits in registers and an adde $r_tractor to calculate a partial product or a partial remainder, the hardware overhead can be greatly reduced. In addition, the proposed architecture can perform an additio $n_traction and a shift operation in parallel and the number of cycles for $\textit{N}$-bit multiplication and division for the proposed circuits is $\textit{N}$ and $\textit{N}$ + 2, repectively. Thus, the number of cycles for multiplication and division is the same compared with existing architectures. The SliM Image Processor employs the proposed multiplier/divider architecture and proves the performance of the proposed architecture.cture.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.3 s.357
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• pp.35-42
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• 2007

The finite-field division can be applied to the elliptic curve cryptosystems. However, an efficient algorithm and the hardware design are required since the finite-field division takes much time to compute. In this paper, we propose a radix-4 systolic divider on $GF(2^m)$ with comparative area and performance. The algorithm of the proposed divide, is mathematically developed and new counter structure is proposed to map on low-cost systolic cells, so that the proposed systolic architecture is suitable for YLSI design. Compared to the bit-parallel, bit-serial and digit-serial dividers, the proposed divider has relatively effective high performance and low cost. We design and synthesis $GF(2^{193})$ finite-field divider using Dongbuanam $0.18{\mu}m$ standard cell library and the maximum clock frequency is 400MHz.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.14 no.6
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• pp.117-124
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• 2015

In this paper, a new kind of wideband, low-loss composite right/left-handed (CRLH) transmission line (TL) and a Wilkinson power divider are presented. The TL is composed of a parallel meander inductor and a series cutting capacitor based on coplanar waveguide (CPW) structure. The power divider is designed by substituting the CRLH-TL into the conventional transmission line. The experiment results show that the TL has a good agreement with the desired results, exhibiting the return losses under 12 dB from 8.4 GHz to 34.4 GHz. The operating frequencies of the power divider are 12.05 GHz to 13.15 GHz and 16.50 GHz to 19.30 GHz, respectively. The 20 dB bandwidths are 8.9 % and 17.9 %, respectively. Typical experimental measurements are conducted and compared with the simulated results.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.47 no.5
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• pp.199-205
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• 2010

In this paper, we proposed a polyphase encoder that consists of multiple internal encoders. The multiple internal encoders were configured in parallel. Successive frames of image were distributed to separate encoders by way of a image divider and processed in parallel. In this way, the sampling rate of the encoder was reduced by the factor of number of encoders in parallel. In our design, however, the PSNR is exactly the same as that to be achieved with the conventional single-phase encoder, which should require a much higher sampling rate.