• KSII Transactions on Internet and Information Systems (TIIS)
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• v.16 no.5
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• pp.1611-1633
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• 2022

At EUROCRYPT 2019, a new block cipher algorithm called BISON was proposed by Canteaut et al. which uses a novel structure named as Whitened Swap-Or-Not (WSN). Unlike the traditional wide trail strategy, the differential and linear properties of this algorithm can be easily determined. However, the encryption speed of the BISON algorithm is quite low due to a large number of iterative rounds needed to ensure certain security margins. Commonly, denoting by n is the data block length, this design requires 3n encryption rounds. Moreover, the block size n of BISON is always odd, which is not convenient for operations performed on a byte level. In order to overcome these issues, we propose a new block cipher, named DBISON, which more efficiently employs the ideas of double layers typical to the BISON-like construction. More precisely, DBISON divides the input into two parts of size n/2 bits and performs the round computations in parallel, which leads to an increased encryption speed. In particular, the data block length n of DBISON can be even, which gives certain additional implementation benefits over BISON. Furthermore, the resistance of DBISON against differential and linear attacks is also investigated. It is shown the maximal differential probability (MDP) is 1/2^n-1 for n encryption rounds and that the maximal linear probability (MLP) is strictly less than 1/2^n-1 when (n/2+3) iterative encryption rounds are used. These estimates are very close to the ideal values when n is close to 256.

• The KIPS Transactions:PartD
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• v.10D no.6
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• pp.935-948
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• 2003

An online scaling method adds new nodes to the shared-nothing database cluster and makes tables be reorganized while the system is running. The objective is to share the workload with many nodes and increase the capacity of cluster systems. The existing online scaling method, however, has two problems. One is the degradation of response time and transactions throughput due to the additional overheads of data transfer and replica's condidtency. The other is and inefficient recovery mechanism in which the overall scaling transaction is aborted by a fault. These problems deteriorate the availability of shared-nothing database cluster. To avoid the additional overheads throughout the scaling period, our scalingmethod consists of twophases : a parallel data transfer phase and a combination phase. The parallel data transferred datausing reduces the size of data transfer by dividing the data into the number of replicas. The combination phase combines the transferred datausing resources of spare nodes. Also, our method reduces the possibility of failure throughout the scaling period and improves the availability of the database cluster.

• Journal of the Korea Society of Computer and Information
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• v.19 no.10
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• pp.1-12
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• 2014

This paper implements and improves the performance of high computational subtractive clustering algorithm using a single instruction, multiple data (SIMD) based many-core processor. In addition, this paper implements five different processing element (PE) architectures (PEs=16, 64, 256, 1,024, 4,096) to select an optimal PE architecture for the subtractive clustering algorithm by estimating execution time and energy efficiency. Experimental results using two different medical images and three different resolutions ($128{\times}128$, $256{\times}256$, $512{\times}512$) show that PEs=4,096 achieves the highest performance and energy efficiency for all the cases.

• Journal of Convergence for Information Technology
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• v.9 no.7
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• pp.33-40
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• 2019

As aerospace industry has been activated recently, it is required to commercialize composite analysis software. Until now, commercial software has been mainly used for analyzing composites, but it has been difficult to use due to high price and limited functions. In order to solve this problem, automatic analysis software for both in-plane and corner radius strength, which are all made on-line and generalized, has recently been developed. However, these have the disadvantage that they can not be analyzed simultaneously with multiple failure criteria. In this paper, we propose a method to greatly improve the processing speed while simultaneously handling the analysis of multiple failure criteria using a parallel processing platform that only works with a GPU equipped with a CUDA core. We have obtained satisfactory results when the analysis speed is experimented on the vast structure data.

• The KIPS Transactions:PartA
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• v.14A no.1 s.105
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• pp.55-62
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• 2007

Uptime of embedded processors for mobile devices are dependent on battery consumption. Especially the large portion of power consumption is known to be due to cache management in embedded processors. This paper proposes an energy efficient data cache structure for high performance embedded processors. High performance prefetching data cache issues prefetching instructions before issuing demand-fetch instructions based on reference predictions. These prefetching instruction bring reduction on memory delay by improving cache hit ratio, but on the other hand those increase energy consumption in proportion to the number of prefetching instructions. In this paper, we adopt tag history table on prefetching data cache for reducing energy consumption by minimizing parallel tag comparison. Experimental results show the proposed data cache improves performance on energy consumption as well as memory delay.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.48 no.4
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• pp.1-8
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• 2011

Traditional transactional memory systems are no longer able to guarantee the performance of diverse applications with overflowed transactions since there is the drawback that tracking the data for logging is difficult. Especially, this mechanism has a disadvantage of increasing communication delay for sustaining the state which is required to detect the conflict on the overflowed transactions from the first level cache in the transactional memory systems. To address this point, we have focused on the cache architecture of the systems to reduce the overhead caused by overflows and cache misses. In this paper, we present Supportive Cache which reduces additional overhead during transactions. Supportive Cache performs a parallel look-up with L1 private cache and uses the same replacement policy as L1 private cache. We evaluate the performance of the proposed design by comparing LogTM-SE with and without Supportive Cache. The simulation results show that our system improves the performance by 37% on average, compared to the original LogTM-SE which uses the same hardware resource.

• Explosives and Blasting
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• v.21 no.4
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• pp.11-21
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• 2003

An experimental study was carried out in order to reduce the period and cost of construction of Missiryung tunnel, which is a relatively long one 3.6 km long. An allowable vibration level for curing concrete was established based on the extensive case studies done over the world. and assessment was performed on the possibility of constructing concrete structures like lining during tunnel blasting. Attenuation relationships were obtained by processing more than 130 measurement data from a series of tunnel blasting in the site. A Guideline for safe construction work was suggested. To verification, low small concrete blocks with a constant standoff distance were installed in the floor of the tunnel After the blocks were exposed to blast vibrations for 28 days, compressive strength tests were performed on 20 specimens taken from the blocks. It was shown that the suggested guideline was appropriate for the safe construction work at the site.

• Journal of KIISE
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• v.44 no.1
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• pp.78-83
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• 2017

Finding the densest subgraphs from social networks, such that people in the subgraph are in a particular community or have common interests, has been a recurring problem in numerous studies undertaken. However, these algorithms focused only on finding the single densest subgraph. We suggest a heuristic algorithm of the bottom-up type, which finds the densest subgraph by increasing its size from a given starting node, with the repeated addition of adjacent nodes with the maximum degree. Furthermore, since this approach matches well with parallel processing, we further implement a parallel algorithm on the MapReduce framework. In experiments using various graph data, we confirmed that the proposed algorithm finds the densest subgraphs in fewer steps, as compared to other related studies. It also scales efficiently for many given starting nodes.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.7 s.337
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• pp.27-36
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• 2005

This paper presents an area-efficient architecture to implement the high-speed Reed-Solomon(RS) decoder, which is used in a variety of communication systems such as wireless and very high-speed optical communications. We present the new pipelined-recursive Modified Euclidean(PrME) architecture to achieve high-throughput rate and reducing hardware-complexity using folding technique. The proposed pipelined recursive architecture can reduce the hardware complexity about 80$\%$ compared to the conventional systolic-array and fully-parallel architecture. The proposed RS decoder has been designed and implemented with the 0.13um CMOS technology in a supply voltage of 1.2 V. The result show that total number of gate is 393 K and it has a data processing rate of S Gbits/s at clock frequency of 625 MHz. The proposed area-efficient architecture can be readily applied to the next generation FEC devices for high-speed optical communications as well as wireless communications.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.2
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• pp.257-263
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• 2002

A graph embedding problem has been studied for applications of resource allocation and mapping the underlying data structure of a parallel algorithm into the interconnection architecture of massively parallel processing systems. In this paper, we consider the embedding problem of the pyramid into the regular 2-dimensional mesh interconnection network topology. We propose a new embedding function which can embed the pyramid of height N into 2$^{N}$ x2$^{N}$ 2-dimensional mesh with dilation max{2$^{N1}$-2. [3.2$^{N4}$＋1)/2, 2$^{N3}$＋2. [3.2$^{N4}$＋1)/2]}. This means an improvement in the dilation measure from 2$^{N}$ $^1$in the previous result into about (5/8) . 2$^{N1}$ under the same condition.condition.