• Title/Summary/Keyword: Parallel data processing

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An Implementation of Real-time Image Warping Using FPGA (FPGA를 이용한 실시간 영상 워핑 구현)

  • Ryoo, Jung Rae;Lee, Eun Sang;Doh, Tae-Yong
    • IEMEK Journal of Embedded Systems and Applications
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    • v.9 no.6
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    • pp.335-344
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    • 2014
  • As a kind of 2D spatial coordinate transform, image warping is a basic image processing technique utilized in various applications. Though image warping algorithm is composed of relatively simple operations such as memory accesses and computations of weighted average, real-time implementations on embedded vision systems suffer from limited computational power because the simple operations are iterated as many times as the number of pixels. This paper presents a real-time implementation of a look-up table(LUT)-based image warping using an FPGA. In order to ensure sufficient data transfer rate from memories storing mapping LUT and image data, appropriate memory devices are selected by analyzing memory access patterns in an LUT-based image warping using backward mapping. In addition, hardware structure of a parallel and pipelined architecture is proposed for fast computation of bilinear interpolation using fixed-point operations. Accuracy of the implemented hardware is verified using a synthesized test image, and an application to real-time lens distortion correction is exemplified.

An embedded vision system based on an analog VLSI Optical Flow vision sensor

  • Becanovic, Vlatako;Matsuo, Takayuki;Stocker, Alan A.
    • Proceedings of the Korea Society of Information Technology Applications Conference
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    • 2005.11a
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    • pp.285-288
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    • 2005
  • We propose a novel programmable miniature vision module based on a custom designed analog VLSI (aVLSI) chip. The vision module consists of the optical flow vision sensor embedded with commercial off-the-shelves digital hardware; in our case is the Intel XScale PXA270 processor enforced with a programmable gate array device. The aVLSI sensor provides gray-scale imager data as well as smooth optical flow estimates, thus each pixel gives a triplet of information that can be continuously read out as three independent images. The particular computational architecture of the custom designed sensor, which is fully parallel and also analog, allows for efficient real-time estimations of the smooth optical flow. The Intel XScale PXA270 controls the sensor read-out and furthermore allows, together with the programmable gate array, for additional higher level processing of the intensity image and optical flow data. It also provides the necessary standard interface such that the module can be easily programmed and integrated into different vision systems, or even form a complete stand-alone vision system itself. The low power consumption, small size and flexible interface of the proposed vision module suggests that it could be particularly well suited as a vision system in an autonomous robotics platform and especially well suited for educational projects in the robotic sciences.

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Design and implementation of the SliM image processor chip (SliM 이미지 프로세서 칩 설계 및 구현)

  • 옹수환;선우명훈
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.33A no.10
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    • pp.186-194
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    • 1996
  • The SliM (sliding memory plane) array processor has been proposed to alleviate disadvantages of existing mesh-connected SIMD(single instruction stream- multiple data streams) array processors, such as the inter-PE(processing element) communication overhead, the data I/O overhead and complicated interconnections. This paper presents the deisgn and implementation of SliM image processor ASIC (application specific integrated circuit) chip consisting of mesh connected 5 X 5 PE. The PE architecture implemented here is quite different from the originally proposed PE. We have performed the front-end design, such as VHDL (VHSIC hardware description language)modeling, logic synthesis and simulation, and have doen the back-end design procedure. The SliM ASIC chip used the VTI 0.8$\mu$m standard cell library (v8r4.4) has 55,255 gates and twenty-five 128 X 9 bit SRAM modules. The chip has the 326.71 X 313.24mil$^{2}$ die size and is packed using the 144 pin MQFP. The chip operates perfectly at 25 MHz and gives 625 MIPS. For performance evaluation, we developed parallel algorithms and the performance results showed improvement compared with existing image processors.

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Cloud-based Intelligent Management System for Photovoltaic Power Plants (클라우드 기반 태양광 발전단지 통합 관리 시스템)

  • Park, Kyoung-Wook;Ban, Kyeong-Jin;Song, Seung-Heon;Kim, Eung-Kon
    • The Journal of the Korea institute of electronic communication sciences
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    • v.7 no.3
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    • pp.591-596
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    • 2012
  • Recently, the efficient management system for photovoltaic power plants has been required due to the continuously increasing construction of photovoltaic power plants. In this paper, we propose a cloud-based intelligent management system for many photovoltaic power plants. The proposed system stores the measured data of power plants using Hadoop HBase which is a column-oriented database, and processes the calculations of performance, efficiency, and prediction the amount of power generation by parallel processing based on Map-Reduce model. And, Web-based data visualization module allows the administrator to provide information in various forms.

The study on the Efficient methodology to apply the GPU for military information system improvement (국방정보시스템 성능향상을 위한 효율적인 GPU적용방안 연구)

  • Kauh, Janghyuk;Lee, Dongho
    • Journal of Korea Society of Digital Industry and Information Management
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    • v.11 no.1
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    • pp.27-35
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    • 2015
  • Increasing the number of GPU (Graphic Processor Unit) cores, the studies on High Performance Computing Platform using GPU have actively been made in recent. This trend has led to the development of GPGPU (General Purpose GPU) and CUDA (Compute Unified Device Architecture) Framework. In this paper, we explain the many benefits of the GPU based system, and propose the ICIDF(Identify Compute-Intensive Data set and Function) methodology to apply GPU technology to legacy military information system for performance improvement. To demonstrate the efficiency of this methodology, we applied this method to AES CPU based program obtained from the Internet web site. Simply changing the data structure made improved the performance of AES program. As a result, the performance of AES based GPU program is improved gradually up to 10 times. Depending on the developer's ability, additional performance improvement can be expected. The problem to be solved is heat issue, but this problem has been much improved by the development of the cooling technology.

Volume holographic correlator for fingerprint recognition (지문 인식을 위한 체적 홀로그래픽 광상관기)

  • 이승현;김은수
    • Korean Journal of Optics and Photonics
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    • v.9 no.6
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    • pp.385-389
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    • 1998
  • In this paper, we propose an optical correlator system using volume holograms for database of matched filters. Optical correlator has high speed and parallel processing characteristics of optics. Matched filters are recorded into a volume hologram that can store data with high density, transfer them with high speed, and select a randomly chosen data element. The multiple reference images of database are prerecorded in a photorefractive crystal in the form of Fourier transform images, simply by passing the image displayed in a spatial light modulator through a Fourier transform lens. The angular multiplexing method for multiple holograms of database can be achieved by rotating the crystal by use of a step motor. Experimental results show that the proposed system can be used for the fingerprint recognition.

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Program Slicing in the Presence of Complicated Data Structure (복잡한 자료 구조를 지니는 프로그램 슬라이싱)

  • Ryu, Ho-Yeon;Park, Joong-Yang;Park, Jae-Heung
    • The KIPS Transactions:PartD
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    • v.10D no.6
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    • pp.999-1010
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    • 2003
  • Program slicing is s method to extract the statements from the program which have an influence on the value of a variable at a paricular point of the program. Program slicing is applied for many applications, such as program degugging, program testing, program integration, parallel program execution, software metrics, reverse engineering, and software maintenance, etc. This paper is the study to create the exact slice in the presence of Object Reference State Graph to generate more exactly static analysis information of objects in the program of the presence of complicated data structure.

Improved Physical Layer Implementation of VANETs

  • Khan, Latif Ullah;Khattak, M. Irfan;Khan, Naeem;Khan, Atif Sardar;Shafi, M.
    • IEIE Transactions on Smart Processing and Computing
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    • v.3 no.3
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    • pp.142-152
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    • 2014
  • Vehicular Ad-hoc Networks (VANETs) are comprised of wireless mobile nodes characterized by a randomly changing topology, high mobility, availability of geographic position, and fewer power constraints. Orthogonal Frequency Division Multiplexing (OFDM) is a promising candidate for the physical layer of VANET because of the inherent characteristics of the spectral efficiency and robustness to channel impairments. The susceptibility of OFDM to Inter-Carrier Interference (ICI) is a challenging issue. The high mobility of nodes in VANET causes higher Doppler shifts, which results in ICI in the OFDM system. In this paper, a frequency domain com-btype channel estimation was used to cancel out ICI. The channel frequency response at the pilot tones was estimated using a Least Square (LS) estimator. An efficient interpolation technique is required to estimate the channel at the data tones with low interpolation error. This paper proposes a robust interpolation technique to estimate the channel frequency response at the data subcarriers. The channel induced noise tended to degrade the Bit Error Rate (BER) performance of the system. Parallel concatenated Convolutional codes were used for error correction. At the decoding end, different decoding algorithms were considered for the component decoders of the iterative Turbo decoder. A performance and complexity comparison among the various decoding algorithms was also carried out.

User-based Collaborative Filtering Recommender Technique using MapReduce (맵리듀스를 이용한 사용자 기반 협업 필터링 추천 기법)

  • Yun, So-young;Youn, Sung-dae
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2015.10a
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    • pp.331-333
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    • 2015
  • Data is increasing explosively with the spread of networks and mobile devices and there are problems in effectively processing the rapidly increasing data using existing recommendation techniques. Therefore, researches are being conducted on how to solve the scalability problem of the collaborative filtering technique. In this paper applies MapReduce, which is a distributed parallel process framework, to the collaborative filtering technique to reduce the scalability problem and heighten accuracy. The proposed technique applies MapReduce and the index technique to a user-based collaborative filtering technique and as a method which improves neighbor numbers which are used in similarity calculations and neighbor suitability, scalability and accuracy improvement effects can be expected.

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MRSPAKE : A Web-Scale Spatial Knowledge Extractor Using Hadoop MapReduce (MRSPAKE : Hadoop MapReduce를 이용한 웹 규모의 공간 지식 추출기)

  • Lee, Seok-Jun;Kim, In-Cheol
    • KIPS Transactions on Software and Data Engineering
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    • v.5 no.11
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    • pp.569-584
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    • 2016
  • In this paper, we present a spatial knowledge extractor implemented in Hadoop MapReduce parallel, distributed computing environment. From a large spatial dataset, this knowledge extractor automatically derives a qualitative spatial knowledge base, which consists of both topological and directional relations on pairs of two spatial objects. By using R-tree index and range queries over a distributed spatial data file on HDFS, the MapReduce-enabled spatial knowledge extractor, MRSPAKE, can produce a web-scale spatial knowledge base in highly efficient way. In experiments with the well-known open spatial dataset, Open Street Map (OSM), the proposed web-scale spatial knowledge extractor, MRSPAKE, showed high performance and scalability.