• Journal of the Korean Institute of Telematics and Electronics S
• /
• v.35S no.4
• /
• pp.96-104
• /
• 1998

In this paper, the circuit of DTCNN designed using dilation and erosion operation, a basic operation of gray-scale morphology, also each cell designed PE in order to having extension using the local connectivity. In this PE design, connection of between cell and cell become simple. And it is realized to easily VLSI realization as well as to circuit to be parallel processing. As the resutls of simulations, the proposed method was verified to improved more operation speed than the sequential data processing, parallel processing DTCNN was implemented in a 0.8.mu.m CMOS technology using COMPASS Tool.

• Journal of the Korean Society for Railway
• /
• v.8 no.1
• /
• pp.1-5
• /
• 2005

This paper has presented the parallel cyclic redundancy check (CRC) technique that performs CRC computation in parallel superior to the conventional CRC technique that processes data bits serially. Also, it has showed that the implemented parallel CRC circuit has been successfully applied to the inductively coupled passive RFTD system working at a frequency of 13.56㎒ in order to process the detection of logical faults more fast and the system has been verified experimentally. In comparison with previous works, the proposed RFID system using the parallel CRC technique has been shown to reduce the latency and increase the data processing rates about 15％ In the results. Therefore, it seems reasonable to conclude that the parallel CRC realization in the RFID system offers a means of maintaining the integrity of data in the high speed RFID system.

• Journal of the Korea Society of Computer and Information
• /
• v.16 no.10
• /
• pp.11-21
• /
• 2011

This paper introduces an SIMD(Single Instruction Multiple Data) based parallel processor that efficiently processes massive data inherent in multimedia. In addition, this paper implements MMX(MultiMedia eXtension)-type instructions on the data parallel processor and evaluates and analyzes the performance of the MMX-type instructions. The reference data parallel processor consists of 16 processors each of which has a 32-bit datapath. Experimental results for a JPEG compression application with a 1280x1024 pixel image indicate that MMX-type instructions achieves a 50% performance improvement over the baseline instructions on the same data parallel architecture. In addition, MMX-type instructions achieves 100% and 51% improvements over the baseline instructions in energy efficiency and area efficiency, respectively. These results demonstrate that multimedia specific instructions including MMX-type have potentials for widely used many-core GPU(Graphics Processing Unit) and any types of parallel processors.

• Proceedings of the IEEK Conference
• /
• 2000.07a
• /
• pp.429-432
• /
• 2000

The new MPEG-4 video coding standard enables content-based functionalities. In order to support the philosophy of the MPEG-4 visual standard, each frame of video sequences should be represented in terms of video object planes (VOP’s). In other words, video objects to be encoded in still pictures or video sequences should be prepared before the encoding process starts. Therefore, it requires a prior decomposition of sequences into VOP’s so that each VOP represents a moving object. A parallel processing system is required an automatic segmentation to be processed in real-time, because an automatic segmentation is time consuming. This paper addresses the parallel processing: system for an automatic segmentation for separating moving object from the background in image sequences. The proposed parallel processing system comprises of processing elements (PE’s) and a multi-access memory system (MAMS). Multi-access memory system is a memory controller to perform parallel memory access with the variety of types: horizontal, vertical, and block access way. In order to realize these ways, a multi-access memory system consists of a memory module selection module, data routing modules, and an address calculation and routing module. The proposed system is simulated and evaluated by the CADENCE Verilog-XL hardware simulation package.

• 제어로봇시스템학회:학술대회논문집
• /
• 2005.06a
• /
• pp.864-867
• /
• 2005

In this paper we introduce a design of parallel architecture for wavelet transformation on FPGA. We implement wavelet transforms though lifting scheme and apply Daubechies4 transform equations. This technique has an advantage that we can obtain perfect reconstruction of the data. We divide our process to high pass filter and low pass filter. With this division, we can find coefficients from low and high pass filters simultaneously using parallel processing properties of FPGA to reduce processing time. From the equations, we have to design real number computation module, referred to IEEE754 standard. We choose 32 bit computation that is fine enough to reconstruct data. After that we arrange the real number module according to Daubechies4 transform though lifting scheme.

• Proceedings of the IEEK Conference
• /
• 1998.06a
• /
• pp.62-65
• /
• 1998

This paper presents a method and implementation of the parallel distributed sample scrambler(DSS) in the cell-based ATM transmission environment. In the serial processing, it requires very high speed clock because the processing clock of the serial DSS is equal with the data transmission speed. In this paper, we develop a conversion method of the serial SRG(shift register generator) to 8bit parallel realization. In this case, it has a sample data processing problem which is a character of DSS. So, a theory of correction time movement is presented to solve this problem. We has developed a ASIC using this algorithm and verified the recommendation of ITU-T, I.432.

• International Journal of Fuzzy Logic and Intelligent Systems
• /
• v.4 no.1
• /
• pp.50-55
• /
• 2004

We propose an intgrated Gill environment system having only integer fuzzy operations in the consequent part and the defuzzification stage. In this paper, we also propose an integrated Gill environment system with 4 parallel fuzzy processing units to be operated in parallel on the classification of the sensed image data. In this, we solve the problems of taking longer times as the fuzzy real computations of [0, 1] by using the integer pixel conversion algorithm to convert lines of each fuzzy linguistic term to the closest integer pixels. This procedure is performed automatically in the GUI application program. As a Gill environment, PCI transmission, image data pre-processing, integer pixel mapping and fuzzy membership tuning are considered. This system can be operated in parallel manner for MIMO or MISO systems.

• Journal of the Korean Data and Information Science Society
• /
• v.17 no.1
• /
• pp.13-18
• /
• 2006

The purpose of this paper is to identify optimal designs of server port connections between two server system for 200-300 user group. Given 3 empirical models as user and port parallel server types under some conditions of 100 Mbps and optimal CPU temperature suggested by Lee and Kim(2005), our results are shown; port parallel model was optimal when traffic processing times measured, and 250 traffics was jumping point as a critical point in our cases.

• Applied Microscopy
• /
• v.46 no.1
• /
• pp.6-13
• /
• 2016

Fluorescence lifetime imaging microscopy (FLIM) has been considered an effective technique to investigate chemical properties of the specimens, especially of biological samples. Despite of this advantageous trait, researchers in this field have had difficulties applying FLIM to their systems because acquiring an image using FLIM consumes too much time. Although analog mean-delay (AMD) method was introduced to enhance the imaging speed of commonly used FLIM based on time-correlated single photon counting (TCSPC), a real-time image reconstruction using AMD method has not been implemented due to its data processing obstacles. In this paper, we introduce a real-time image restoration of AMD-FLIM through fast parallel data processing by using Threading Building Blocks (TBB; Intel) and octa-core processor (i7-5960x; Intel). Frame rate of 3.8 frames per second was achieved in $1,024{\times}1,024$ resolution with over 4 million lifetime determinations per second and measurement error within 10%. This image acquisition speed is 184 times faster than that of single-channel TCSPC and 9.2 times faster than that of 8-channel TCSPC (state-of-art photon counting rate of 80 million counts per second) with the same lifetime accuracy of 10% and the same pixel resolution.

• Journal of the Korean Data and Information Science Society
• /
• v.24 no.5
• /
• pp.1043-1061
• /
• 2013

Recent advances in computer technology introduce massive data and their analysis becomes important. The high performance computing is one of the most essential part in analysis of massive data. In this paper, we review the general purpose of the graphics processing unit and its application to parallel computing, which has been of great interest in statistics communities.