• Progress in Superconductivity
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• v.1 no.1
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• pp.68-72
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• 1999

Since the discovery of high Tc superconductors, great efforts have been focused to develop high performance HTS magnets for the ultimate applications to power system devices. Magnet designers, however, have had difficulties in the estimation of the maximum operating current of the designed magnet from the tested short sample data, due to the degradation of the critical current density in the magnet. Similar story applies to the HTS electrical bus bar. It has been found that the critical current of Bi-2223 stacked tapes is much less than the total summation of critical currents of each tape, which is mainly attributed to the self magnetic fields. Furthermore, since the critical current degradation of Bi-2223 tape is greater in the normal magnetic field (to the tape surface) than in the parallel one, detailed magnetic field configurations are required to reduce the self field effects. In this paper, we calculate the self field effects of a stacked conductor, defining self field factors of normal and parallel magnetic fields to the tape surface. Finally, the critical current degradations in the HTS magnet are explained by the introduced self field factors of the stacked conductor.

• ETRI Journal
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• v.32 no.1
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• pp.73-83
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• 2010

Combinatorial testing has been an active research area in recent years. One challenge in this area is dealing with the combinatorial explosion problem, which typically requires a very expensive computational process to find a good test set that covers all the combinations for a given interaction strength (t). Parallelization can be an effective approach to manage this computational cost, that is, by taking advantage of the recent advancement of multicore architectures. In line with such alluring prospects, this paper presents a new deterministic strategy, called multicore modified input parameter order (MC-MIPOG) based on an earlier strategy, input parameter order generalized (IPOG). Unlike its predecessor strategy, MC-MIPOG adopts a novel approach by removing control and data dependency to permit the harnessing of multicore systems. Experiments are undertaken to demonstrate speedup gain and to compare the proposed strategy with other strategies, including IPOG. The overall results demonstrate that MC-MIPOG outperforms most existing strategies (IPOG, IPOF, IPOF2, IPOG-D, ITCH, TConfig, Jenny, and TVG) in terms of test size within acceptable execution time. Unlike most strategies, MC-MIPOG is also capable of supporting high interaction strengths of t > 6.

• Proceedings of the IEEK Conference
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• summer
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• pp.103-109
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• 2004

In NLP (Natural Language Processing) tasks, the highest difficulty which computers had to face with, is the built-in ambiguity of Natural Languages. To disambiguate it, formerly, they based on human-devised rules. Building such a complete rule-set is time-consuming and labor-intensive task whilst it doesn't cover all the cases. Besides, when the scale of system increases, it is very difficult to control that rule-set. So, recently, many NLP tasks have changed from rule-based approaches into corpus-based approaches with large annotated corpora. Corpus-based NLP tasks for such popular languages as English, French, etc. have been well studied with satisfactory achievements. In contrast, corpus-based NLP tasks for Vietnamese are at a deadlock due to absence of annotated training data. Furthermore, hand-annotation of even reasonably well-determined features such as part-of-speech (POS) tags has proved to be labor intensive and costly. In this paper, we present our building an annotated English-Vietnamese parallel aligned corpus named EVC to train for Vietnamese-related NLP tasks such as Word Segmentation, POS-tagger, Word Order transfer, Word Sense Disambiguation, English-to-Vietnamese Machine Translation, etc.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.7
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• pp.251-257
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• 2014

The Viterbi algorithm(VA) is used to estimate the state transition of discrete-time finite state machine(FSM) that is in an uncorrelated noisy environment. This paper modified the Hamming Network to estimate the state transitions in the finite state machines, and proposed state-parallel and block-parallel Viterbi decoder. The modified Hamming Network(mHN) can perform the decoding of convolutional codes correctly as conventional Viterbi decoder. Furthermore, the complexities of the proposed Viterbi decoder are reduced approximately 10% less than conventional Viterbi decoder, and the processing times are improved approximately 40% more than conventional Viterbi decoder.

• Journal of Digital Contents Society
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• v.18 no.7
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• pp.1341-1346
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• 2017

In this paper, we designed the open service platform based on integrated type of individual customized service and intelligent information technology with individual's complex attributes and requests. First, the data collection phase is proceed quickly and accurately to repeat extraction, transformation and loading. The generated data from extraction-transformation-loading process module is stored in the distributed data system. The data analysis phase is generated a variety of patterns that used the analysis algorithm in the field. The data processing phase is used distributed parallel processing to improve performance. The data providing should operate independently on device-specific management platform. It provides a type of the Open API.

• Journal of Korea Society of Digital Industry and Information Management
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• v.7 no.4
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• pp.119-131
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• 2011

In this paper, we explore the application of 2-D dual-tree discrete wavelet transform (DDWT), which is a directional and redundant transform, for image coding. DDWT main property is a more computationally efficient approach to shift invariance. Also, the DDWT gives much better directional selectivity when filtering multidimensional signals. The dual-tree DWT of a signal is implemented using two critically-sampled DWTs in parallel on the same data. The transform is 2-times expansive because for an N-point signal it gives 2N DWT coefficients. If the filters are designed is a specific way, then the sub-band signals of the upper DWT can be interpreted as the real part of a complex wavelet transform, and sub-band signals of the lower DWT can be interpreted as the imaginary part. The quincunx lattice is a sampling method in image processing. It treats the different directions more homogeneously than the separable two dimensional schemes. Quincunx lattice yields a non separable 2D-wavelet transform, which is also symmetric in both horizontal and vertical direction. And non-separable wavelet transformation can generate sub-images of multiple degrees rotated versions. Therefore, non-separable image processing using DDWT services good performance.

• Proceedings of the IEEK Conference
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• summer
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• pp.391-394
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• 2004

This paper focuses on the DSP implementation of an HMM-based speech recognizer that can handle several hundred words of vocabulary size as well as speaker independency. First, we develop an HMM-based speech recognition system on the PC that operates on the frame basis with parallel processing of feature extraction and Viterbi decoding to make the processing delay as small as possible. Many techniques such as linear discriminant analysis, state-based Gaussian selection, and phonetic tied mixture model are employed for reduction of computational burden and memory size. The system is then properly optimized and compiled on the TMS320C6711 DSP for real-time operation. The implemented system uses 486kbytes of memory for data and acoustic models, and 24.5kbytes for program code. Maximum required time of 29.2ms for processing a frame of 32ms of speech validates real-time operation of the implemented system.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.22 no.3
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• pp.31-36
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• 2022

Recently, drones are being used in various fields, and drone technology is also developing. The risks of drones are increasing, then technology to detect drones is important. However, it is extremely difficult to detect and recognize drones due to the low level radar cross section of the commercial drones. In this paper, a signal processor structure that was mounted the miniaturized and light-weighted was designed. in order to process large amounts of data in real time, parallel processing was performed for each channel and an algorithm was applied to shorten the operation time in each step. As a test of verifing the detection performance through test, it was confirmed that the structure design works in real time.

• 한국신재생에너지학회:학술대회논문집
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• 2008.10a
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• pp.208-212
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• 2008

Gas hydrate has been paid attention to study for because: 1) it can be considered as a new energy resources; 2) one of reasons causing the instability of sea floor slope and 3) a factor to the climate change. Bottom simulating reflector (BSR) defined as seismic boundary between the gas hydrate and free gas zone has been considered as the most common evidence in the seismic reflection data for the gas hydrate exploration. BSR has several characteristics such as parallel to the sea bottom, high amplitude, reducing interval velocity between above and below BSR and reversing phase to the sea bottom. Moreover, instantaneous attribute properties such as amplitude envelop, instantaneous frequency, phase and first derivative of amplitude of seismic data from the complex analysis could be used to analyze properties of BSR those would be added to the certain properties of BSR in order to effectively find out the existence of BSR of the gas hydrate stability zone. The output of conventional seismic data processing for gas hydrate data set in Ulleung basin in the East sea of Korea will be used for complex analyses to indicate better BSR in the seismic reflection data. This result of this analysis implies that the BSR of the analyzed seismic profile is clearly located at the two ways time (TWT) of around 3.1 seconds.

• The KIPS Transactions:PartA
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• v.14A no.5
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• pp.301-308
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• 2007

This paper proposes high performance coprocessor architecture for real time dense disparity computation based on a phase-based binocular stereo matching technique called local weighted phase-correlation(LWPC). The algorithm combines the robustness of wavelet based phase difference methods and the basic control strategy of phase correlation methods, which consists of 4 stages. For parallel and efficient hardware implementation, the proposed architecture employs SIMD(Single Instruction Multiple Data Stream) architecture for each functional stage and all stages work on pipelined mode. Such that the newly devised pipelined linear array processor is optimized for the case of row-column image processing eliminating the need for transposed memory while preserving generality and high throughput. The proposed architecture is implemented with Xilinx HDL tool and the required hardware resources are calculated in terms of look up tables, flip flops, slices, and the amount of memory. The result shows the possibility that the proposed architecture can be integrated into one chip while maintaining the processing speed at video rate.