• Proceedings of the Korean Society of Computer Information Conference
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• 2018.07a
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• pp.1-2
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• 2018

해상 선박의 안전을 위해 해저의 객체 및 장애물의 정확한 탐지를 위해 해저환경에서 감쇠현상이 비교적 적은 음파 기반의 소나가 널리 활용된다. 그러나 기존의 소나 영상 시뮬레이션은 고해상도의 영상, 잡음 처리, 해저지형과 객체 데이터 등의 방대한 데이터 처리로 인해 물체 탐지 및 식별을 위한 처리속도와 비용이 크게 증가한다. 이러한 문제를 최소화하기 위해서 해저지형, 객체 생성과 잡음 처리 모델을 Multi-Threading, SIMD 등 병렬처리를 적용하여 처리속도를 최적화 한다. 본 논문에서는 혼합된 병렬처리 방법을 적용하여 소나를 기반으로 해저 환경 시뮬레이션을 위한 모의 신호를 생성하는 성능을 향상시킨다. 병렬처리로 인해 개선된 성능을 순차처리에 따른 속도와 실험적으로 비교한다.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.30B no.7
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• pp.1-13
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• 1993

In this paper, the problems of the conventional special-purpose array processor such as the deficiency of flexibility have been investigated. Then, a new modified methodology has been suggested and applied to obtain the common solution of the three typical App algorithms like SP(Shortest Path), TC(Transitive Closure), and MST(Minimun Spanning Tree) among the various APP algorithms using the similar method to obtain the solution. In the newly proposed APP parallel algorithm, real-time Processing is possible, without the structure enhancement and the functional restriction. In addition, we design 2-demensional bit-parallel low-triangular systolic array processor and the 1-PE in detail. For its evaluation, we consider its computational complexity according to bit-processing method and describe relationship of total chip size and execution time. Therefore, the proposed processor obtains, on which a large data inputs in real-time, 3n-4 execution time which is optimal o(n) time complexity, o(n$^{2}$) space complexity which is the number of total gate and pipeline period rate is one.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.15 no.7
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• pp.628-637
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• 1990

In this paper we present on architecture for a high sppeed CMOS multiplier which can be used for real-time digital signal processing. And a synthesis method for designing highly parallel algorithms in VLSI is presented. A parallel multiplier design based on the modified Booth's algorithms and Ling's algorthm. This paper addresses the design of multiplier capable of accpting data in 2's complement notation and coefficients in 2's complement notation. Multiplier consists of an interative array of sequential cells, and are well suited to VLSI implementation as a results of their modularity and regularity. Booth's decoders can be fully tested using a relatively small number af test vector.

• Annual Conference of KIPS
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• 2011.04a
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• pp.250-253
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• 2011

Chip manufacture nowadays turned their attention from accelerating uniprocessors to integrating multiple cores on a chip. Moreover desktop graphic hardware is now starting to support general purpose computation. Desktop users are able to use multi-core CPU and GPU as a high performance computing resources these days. However exploiting parallel computing resources are still challenging because of lack of higher programming abstraction for parallel programming. The 2-dimensional discrete cosine transform (2D-DCT) algorithms are most computational intensive part of JPEG encoding. There are many fast 2D-DCT algorithms already studied. We implemented several algorithms and estimated its runtime on multi-core CPU and GPU environments. Experiments show that data parallelism can be fully exploited on CPU and GPU architecture. We expect parallelized DCT bring performance benefit towards its applications such as JPEG and MPEG.

• The Transactions of the Korea Information Processing Society
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• v.3 no.6
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• pp.1433-1442
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• 1996

Data distribution of SPMD(Single Program Multiple Data) pattern is one of main features of HPF (High Performance Fortran). This paper describes design is sues for such data distribution and its efficient execution model on TICOM IV computer, named SPAX(Scalable Parallel Architecture computer based on X-bar network). SPAX has a hierarchical clustering structure that uses distributed shared memory(DSM). In such memory structure, it cannot make a full system utilization to apply unanimously either SMDD(shared Memory Data Distribution) or DMDD(Distributed Memory Data Distribution). Here we propose another data distribution model, called DSMDD(Distributed Shared Memory Data Distribution), a data distribution model based on hierarchical masters-slaves scheme. In this model, a remote master and slaves are designated in each node, shared address scheme is used within a node and message passing scheme between nodes. In our simulation, assuming a node size in which system performance degradation is minimized,DSMDD is more effective than SMDD and DMDD. Especially,the larger number of logical processors and the less data dependency between distributed data,the better performace is obtained.

• Journal of the Korea Society of Computer and Information
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• v.10 no.5 s.37
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• pp.313-322
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• 2005

In this paper, we implement and verify performance monitor for parallel signal processing system, using DSP Starter Kit(DSK) of which the basic Processor is TMS302C6711 chip. The key ideas of this performance monitor is, using Real Time Data Exchange(RTDX) for the Purpose of real-time data transfer and function of DSP/BIOS, the ability to measure the Performance measure like DSP workload, memory usage, and bridge traffic. In the simulation, FFT, 2D FFT, Matrix Multiplication, and Fir Filter, which are widely used DSP algorithms, have been employed. Using performance monitor and Code Composer Studio from Texas Instrument(Tl) , the result has been recorded according to different frequencies, data sizes, and buffer sizes for a single wave file. The accuracy of our performance monitor has been verified by comparing those recorded results.

• Proceedings of the KWS Conference
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• 2002.10a
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• pp.314-319
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• 2002

The Automation and Control Group at the University of Brasilia is developing an automatic welding station based on an industrial robot and a controllable welding machine. Several techniques were applied in order to improve the quality of the welding joints. This paper deals with the implementation of a laser-based computer vision system to guide the robotic manipulator during the welding process. Currently the robot is taught to follow a prescribed trajectory which is recorded a repeated over and over relying on the repeatability specification from the robot manufacturer. The objective of the computer vision system is monitoring the actual trajectory followed by the welding torch and to evaluate deviations from the desired trajectory. The position errors then being transfer to a control algorithm in order to actuate the robotic manipulator and cancel the trajectory errors. The computer vision systems consists of a CCD camera attached to the welding torch, a laser emitting diode circuit, a PC computer-based frame grabber card, and a computer vision algorithm. The laser circuit establishes a sharp luminous reference line which images are captured through the video camera. The raw image data is then digitized and stored in the frame grabber card for further processing using specifically written algorithms. These image-processing algorithms give the actual welding path, the relative position between the pieces and the required corrections. Two case studies are considered: the first is the joining of two flat metal pieces; and the second is concerned with joining a cylindrical-shape piece to a flat surface. An implementation of this computer vision system using parallel computer processing is being studied.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1101-1104
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• 1998

The modern multimedia applications which are video processor, video conference or video phone and so forth require real time processing. Because of a large amount of image data, those require high compression performance. In this paper, the prosposed image processing encoder was designed by using wavelet transform encoding. The proposed filter block can process imae data on the high speed because of composing individual function blocks by parallel and compute both highpass and lowpass coefficient in the same clock cycle. When image data is decomposed into multiresolution, the proposed scheme needs external memory and controller to save intermediate results and it can operate within 33MHz.

• Annual Conference of KIPS
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• 2009.04a
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• pp.834-837
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• 2009

There is a growing need for ad-hoc analysis of extremely large data sets, especially at e-Commerce companies which depend on recommender application. Nowadays, as the number of e-Commerce web pages grow to a tremendous proportion; vertical recommender services can help customers to find what they need. Recommender application is one of the reasons for e-Commerce success in today's world. Compared with general e-Commerce recommender application, obviously, general e-Commerce recommender application's processing scope is greatly narrowed down. MapReduce is emerging as an important programming model for large-scale data-parallel applications such as web indexing, data mining, and scientific simulation. The objective of this paper is to explore MapReduce framework for the e-Commerce recommender application on major general and dedicated link analysis for e-Commerce recommender application, and thus the responding time has been decreased and the recommender application's accuracy has been improved.

• Journal of the Institute of Convergence Signal Processing
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• v.5 no.1
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• pp.40-45
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• 2004

This paper presents the parallel distributed control scheme for shaping of the bent glass. The designed system consists of a PC, a main controller and 11 servo-controllers, the precision motion controllers. Each elements are connected by using RS-232C and 8-bit data bus. In order to guarantee the stability and the control performance, we use a precision PID motion controller and a H-bridge on the servo-drivers. PC calculates position values of 11 DC motors by using the pre-determined curvature value and offers the user interface environment operator. The main controller provides the control instructions and parameter values to 11 servo-controllers by chip enable signal, simultaneously. Using the received commands and parameter values, the servo-controllers control the positions of the DC motors based on PID control scheme.