• The Transactions of the Korea Information Processing Society
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• v.7 no.1
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• pp.74-87
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• 2000

PVM (parallel virtual machine) provides a programming environment that allows a collection of networked workstations to appear as a single parallel computational resource. The performance of parallel applications in this environment depends on the performance of data transfers between tasks. In this paper, we present a new Myrinet-based communication model of PVM that improves PVM communication performance over a high-speed Myrinet LAN. The proposed PVM communication model adopts a communication mechanism that allows any user-level process to directly access the network interface board without going through UDP/IP protocol stacks in the kernel. This mechanism provides faster data transfers between PVM tasks over the Myrinet since it avoids data copy overhead from kernel (user space) to user space (kernel) and reduces communication latency due to network protocol software layers. We implemented EPVM (Enhanced PVM), our updated version of the traditional PVM using UDP/IP, that is based on the proposed communication model over the Myrinet. Performance results show EPVM achieves communication speed-up of one to two over the traditional PVM.

• Journal of the Korean Society of Surveying, Geodesy, Photogrammetry and Cartography
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• v.30 no.2
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• pp.135-142
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• 2012

In the present study, a parallel processing method running on a multi-core PC-Cluster is introduced to produce digital surface model (DSM) and digital terrain model (DTM) from huge airborne laser scanning data. A hybrid model using both message passing interface (MPI) and OpenMP was devised by revising a conventional MPI model which utilizes only MPI, and tested on a multi-core PC-Cluster for performance validation. In the results, the hybrid model has not shown better performances in the interpolation process to produce DSM, but the overall performance has turned out to be better by the help of reduced MPI calls. Additionally, scheduling function of OpenMP has revealed its ability to enhance the performance by controlling inequal overloads charged on cores induced by irregular distribution of airborne laser scanning data.

• The Journal of the Korea Contents Association
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• v.12 no.6
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• pp.1-8
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• 2012

According that most integral imaging techniques have used rectangular lens array, this integrated distribution of light is recorded in the form of a rectangular grid. However, hexagonal lens array gives a more accurate approximation of ideal circular lens and provides higher pickup/display density than rectangular lens array[4]. Using the parallel processing technique in order to generate the elemental imaging for hexagonal lens array, each pixel that compose the elemental imaging should be determined to belong to the hexagonal lens. This process is output to the screen for every pixel in progress, and many computations are required. In this paper, we have proposed parallel processing method using an OpenCL to generate the elemental imaging for hexagonal lens array in 3D volume date. In the experimental result of proposed method show speed of 20~60 fps for hexagonal lens array of $20{\times}20$ sizes and input data of Male[$128{\times}256{\times}256$] volume data.

• Proceedings of the KIEE Conference
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• 1989.11a
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• pp.186-190
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• 1989

A Study for Bad Data Processing in state estimation by a Neural Network is presented. State estimation is the process of assigning a value to an unknown system state variable based on measurement from that system according to some criteria. In this case, the ability to detect and identify bad measurements is extremely valuable, and much time in oder to achieve the state estimation is needed. This paper proposed new bad data processing using Neural Network in order to settle it. The concept of neural net is a parallel distributed processing. In this paper, EBP (Error Back Propagation) algorithm based on three layered feed forward network is used.

• Journal of the Korean Data and Information Science Society
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• v.26 no.5
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• pp.1155-1166
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• 2015

It is almost impossible to store or analyze big data increasing exponentially with traditional technologies, so Hadoop is a new technology to make that possible. In recent R is using as an engine for big data analysis based on distributed processing with Hadoop technology. With RHadoop that integrates R and Hadoop environment, we implemented parallel multiple regression analysis with various data sizes of actual data and simulated data. Experimental results showed our RHadoop system was faster as the number of data nodes increases. We also compared the performance of our RHadoop with lm function and biglm packages available on bigmemory. The results showed that our RHadoop was faster than other packages owing to paralleling processing with increasing the number of map tasks as the size of data increases.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.792-793
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• 2005

Circuit testing process is very important in IC Manufacturing there are two ways in research for circuit testing improvement. These are ATPG Tool Design and Test simulation application. We are interested in how to use parallel technique such as one-side communication, parallel IO and dynamic Process with data partition for circuit testing improvement and we use one-side communication technique in this paper. The parallel ATPG Tool can reduce the test pattern sets of the circuit that is designed in laboratory for make sure that the fault is not occur. After that, we use result for parallel circuit test simulation to find fault between designed circuit and tested circuit. From the experiment, We use less execution time than non-parallel Process. And we can set more parameter for less test size. Previous experiment we can't do it because some parameter will affect much waste time. But in the research, if we use the best ATPG Tool can optimize to least test sets and parallel circuit testing application will not work. Because there are too little test set for circuit testing application. In this paper we use a standard sequential circuit of ISCAS89.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.1
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• pp.49-56
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• 1994

This paper describes the design principles and methods of electronic processor for thermal imager with the SPRITE detector, operating in the 8-12 micron band. The thermal imager consists of a optical scanner containing the detector and an electrical signal processor. The optical scanner utilizing rotating polygon and oscillating mirror, is 2-dimensional serial/parallel scan type using 5 elements of the detector. And the electronic processor has pre-processing of 5 chnanel's thermal signal from the detector, and performs digital scan conversion to reform the parallel data stream into serial analog data compatible with conventional RS-170 video. Through the designed electronic processor, we have acquired a satisfactory thermal image. And the MRTD (Minimum Resolvable Temperature Difference) is 0.5$^{\circ}$K at 7.5 cycles/mm.

• Journal of the Korea Society for Simulation
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• v.3 no.1
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• pp.29-42
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• 1994

The architecture of a MIMD-type parallel computer system is specified: a simulator is developed to support design and evaluation of systems based on the architecture: and conducted with the simulator to evaluate system performance. The horizontal/vertical-bus(H/V-bus) system architecture provides an NxN array of processing elements which communicate with each other through a network of N horizontal buses and N vertical buses. The simulator, written in SLAM II and FORTRAN, is designed to provide high-resolution in simulating the IPC mechanism. Parameters provide the user with independent control of system size, PE speed and IPC mechanism speed. Results generated by the simulator include execution times, PE utilizations, queue lengths, and other data. The simulator is used to study system performance when a partial differential equation is solved by parallel Gauss-Seidel method. For comparisons, the benchmark is also executed on a single-bus system simulator that is derived from the H/V-bus system simulator. The benchmark is also solved on a single PE to obtain data for computing speedups. An extensive analysis of results is presented.

• Journal of the Korea Institute of Military Science and Technology
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• v.13 no.5
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• pp.734-738
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• 2010

Object Generator is a software to provide simulation object data(aircraft, ship, submarine, missile, torpedo) for sumulators in LBTS(Land Based Test System). but there is a burden to the system, because Object generator needs to send many object's data, display objects in a tactical screen, show object's information in a list in 1 second. This paper suggests a parallel software structure taking a few factors(deadlock, dependency) into consideration. At last, the paper shows the performance of the parallel structure's software compared with the former structure's software.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.4
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• pp.93-102
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• 1995

This paper introduces a general purpose Associative Processor(AP) which is very efficient for search-oriented applications. The proposed architecture consists of three main functional blocks: Content-Addressable Memory(CAM) arry, row logic, and control section. The proposed AP is a Single-Instruction, Multiple-Data(SIMD) device based on a CAM core and an array of high speed processors. As an application for the proposed hardware, we present a parallel algorithm to solve a global routing problem in the layout process utilizing the processing capabilities of a rudimentary logic and the selective matching and writing capability of CAMs, along with basic algorithms such a minimum(maximum) search, less(greater) than search and parallel arithmetic. We have focused on the simultaneous minimization of the desity of the channels and the wire length by sedking a less crowded channel with shorter wire distance. We present an efficient mapping technique of the problem into the CAM structure. Experimental results on difficult examples, on randomly generated data, and on benchmark problems from MCNC are included.