• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.3
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• pp.164-173
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• 2014

In underwater robotics, vision would be a key element for recognition in underwater environments. However, due to turbidity an underwater optical camera is rarely available. An underwater imaging sonar, as an alternative, delivers low quality sonar images which are not stable and accurate enough to find out natural objects by image processing. For this, artificial landmarks based on the characteristics of ultrasonic waves and their recognition method by a shape matrix transformation were proposed and were proven in Part 1. But, this is not working properly in undulating and dynamically noisy sea-bottom. To solve this, we propose a framework providing a selection phase of likelihood candidates, a selection phase for final candidates, recognition phase and tracking phase in sequence images, where a particle filter based selection mechanism to eliminate fake candidates and a mean shift based tracking algorithm are also proposed. All 4 steps are running in parallel and real-time processing. The proposed framework is flexible to add and to modify internal algorithms. A pool test and sea trial are carried out to prove the performance, and detail analysis of experimental results are done. Information is obtained from tracking phase such as relative distance, bearing will be expected to be used for control and navigation of underwater robots.

• KSCE Journal of Civil and Environmental Engineering Research
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• v.13 no.2
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• pp.51-59
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• 1993

This paper develops practical and realistic reliability models and methods for the evaluation of system-reliability and system reliability-based rating of various types of box-girder bridge superstructures. The strength limit state model for box-girder bridges suggested in the paper are based on not only the basic flexural strength but also the strength interaction equations which simultaneously take into account flexure, shear and torsion. And the system reliability problem of box-girder superstructure is formulated as parallel-series models obtained from the FMA(Failure Mode Approach) based on major failure mechanisms or critical failure states of each girder. In the paper, an improved IST(Importance Sampling Technique) simulation algorithm is used for the system reliability analysis of the proposed models. This paper proposes a practical but rational approach for the evaluation of capacity rating in terms of the equivalent system-capacity rating corresponding to the estimated system-reliability index which is derived based on the concept of the equivalent FOSM(First Order Second Moment) form of system reliability index. The results of the reliability evaluation and rating of existing bridges indicate that the reserved reliability and capacity rating at system level are significantly different from those of element reliability or conventional methods especially in the case of highly redundant box-girder bridges.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.6
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• pp.447-458
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• 2003

A high speed multiplier is essential basic building block for digital signal processors today. Typically iterative algorithms in Signal processing applications are realized which need a large number of multiply, add and accumulate operations. This paper describes a macro block of a parallel structured multiplier which has adopted a 32$\times$32-b regularly structured tree (RST). To improve the speed of the tree part, modified partial product generation method has been devised at architecture level. This reduces the 4 levels of compression stage to 3 levels, and propagation delay in Wallace tree structure by utilizing 4-2 compressor as well. Furthermore, this enables tree part to be combined with four modular block to construct a CSA tree (carry save adder tree). Therefore, combined with four modular block to construct a CSA tree (carry save adder tree). Therefore, multiplier architecture can be regularly laid out with same modules composed of Booth selectors, compressors and Modified Partial Product Generators (MPPG). At the circuit level new Booth selector with less transistors and encoder are proposed. The reduction in the number of transistors in Booth selector has a greater impact on the total transistor count. The transistor count of designed selector is 9 using PTL(Pass Transistor Logic). This reduces the transistor count by 50% as compared with that of the conventional one. The designed multiplier in 0.25${\mu}{\textrm}{m}$ technology, 2.5V, 1-poly and 5-metal CMOS process is simulated by Hspice and Epic. Delay is 4.2㎱ and average power consumes 1.81㎽/MHz. This result is far better than conventional multiplier with equal or better than the best one published.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.101-111
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• 2008

This paper introduces a high-speed Reed-Solomon(RS) decoder, which reduces the hardware complexity, and presents an RS decoder based FEC architecture which is used for 40Gb/s optical communication systems. We introduce new pipelined degree computationless modified Euclidean(pDCME) algorithm architecture, which has high throughput and low hardware complexity. The proposed 16 channel RS FEC architecture has two 8 channel RS FEC architectures, which has 8 syndrome computation block and shared single KES block. It can reduce the hardware complexity about 30% compared to the conventional 16 channel 3-parallel FEC architecture, which is 4 syndrome computation block and shared single KES block. The proposed RS FEC architecture has been designed and implemented with the $0.18-{\mu}m$ CMOS technology in a supply voltage of 1.8 V. The result show that total number of gate is 250K and it has a data processing rate of 5.1Gb/s at a clock frequency of 400MHz. The proposed area-efficient architecture can be readily applied to the next generation FEC devices for high-speed optical communications as well as wireless communications.

• Journal of the Korean Institute of Intelligent Systems
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• v.18 no.2
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• pp.236-242
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• 2008

In this paper, we propose an optimized fuzzy controller based on Hierarchical Fair Competition-based Genetic Algorithms (HFCGA) for rotary inverted pendulum system. We adopt fuzzy controller to control the rotary inverted pendulum and the fuzzy rules of the fuzzy controller are designed based on the design methodology of Linear Quadratic Regulator (LQR) controller. Simple Genetic Algorithms (SGAs) is well known as optimization algorithms supporting search of a global character. There is a long list of successful usages of GAs reported in different application domains. It should be stressed, however, that GAs could still get trapped in a sub-optimal regions of the search space due to premature convergence. Accordingly the parallel genetic algorithm was developed to eliminate an effect of premature convergence. In particular, as one of diverse types of the PGA, HFCGA has emerged as an effective optimization mechanism for dealing with very large search space. We use HFCGA to optimize the parameter of the fuzzy controller. A comparative analysis between the simulation and the practical experiment demonstrates that the proposed HFCGA based fuzzy controller leads to superb performance in comparison with the conventional LQR controller as well as SGAs based fuzzy controller.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.7 s.361
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• pp.71-80
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• 2007

This paper describes an efficient hardware design of WiBro security processor (WBSec) supporting for the security sub-layer of WiBro wireless internet system. The WBSec processor, which is based on AES (Advanced Encryption Standard) block cipher algorithm, performs data oncryption/decryption, authentication/integrity, and key encryption/decryption for packet data protection of wireless network. It carries out the modes of ECB, CTR, CBC, CCM and key wrap/unwrap with two AES cores working in parallel. In order to achieve an area-efficient implementation, two design techniques are considered; First, round transformation block within AES core is designed using a shared structure for encryption/decryption. Secondly, SubByte/InvSubByte blocks that require the largest hardware in AES core are implemented using field transformation technique. It results that the gate count of WBSec is reduced by about 25% compared with conventional LUT (Look-Up Table)-based design. The WBSec processor designed in Verilog-HDL has about 22,350 gates, and the estimated throughput is about 16-Mbps at key wrap mode and maximum 213-Mbps at CCM mode, thus it can be used for hardware design of WiBro security system.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.19 no.6
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• pp.9-20
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• 2018

When a large-scale photovoltaic (PV) system is introduced into a distribution system, the customer's voltage may exceed the allowable limit ($220V{\pm}6%$) due to voltage variations and reverse power flow in the PV system. In order to solve this problem, we propose a method for adjusting the customer voltage using the existing step voltage regulator (SVR) installed in the primary feeder. However, due to the characteristics of a mechanically operating SVR, the customer voltage during the tap changing time of the SVR is likely to deviate from the allowable limit. In this paper, an energy storage system (ESS) with optimal operation strategies, and an appropriate capacity calculation algorithm are proposed, and the parallel driving scheme between the SVR and the ESS is also proposed to solve the customer voltage problem that may occur during the tap changing time of the SVR. The simulation results show that the allowable limit of the customer voltage is verified by the proposed methods during the tap changing time of the SVR when the large-scale PV system is connected to the distribution system.

• Journal of Korea Multimedia Society
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• v.14 no.5
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• pp.669-680
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• 2011

R-trees are widely used in various areas such as geographical information systems, CAD systems and spatial databases in order to efficiently index multi-dimensional data. As data sets used in these areas grow in size and complexity, however, range query operations on R-tree are needed to be further faster to meet the area-specific constraints. To address this problem, there have been various research efforts to develop strategies for acceleration query processing on R-tree by using the buffer mechanism or parallelizing the query processing on R-tree through multiple disks and processors. As a part of the strategies, approaches which parallelize query processing on R-tree through Graphics Processor Units(GPUs) have been explored. The use of GPUs may guarantee improved performances resulting from faster calculations and reduced disk accesses but may cause additional overhead costs caused by high memory access latencies and low data exchange rate between GPUs and the CPU. In this paper, to address the overhead problems and to adapt GPUs efficiently, we propose a novel approach which uses a GPU as a buffer to parallelize query processing on R-tree. The use of buffer algorithm can give improved performance by reducing the number of disk access and maximizing coalesced memory access resulting in minimizing GPU memory access latencies. Through the extensive performance studies, we observed that the proposed approach achieved up to 5 times higher query performance than the original CPU-based R-trees.

• Journal of Korean Library and Information Science Society
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• v.50 no.1
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• pp.23-41
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• 2019

This study understand the subject domain of book which has been read by men and woman elderly by analizying the PFNET using library big data and confirm the difference between adult at age 30-40. This study extract co-occurrence matrix of book lending on the popular book list from library big data, for 4 group, men/woman elderly, men/woman adult. With these matrix, this study performs FP network analysis. And Pearson Correlation Analysis based on the Triangle Betweenness Centrality calculated on the loan book was performed to understand the correlation among the 4 clusters which has been created by PNNC algorithm. As a result, reading trend which has been focused on modern korean novel has been revealed in elderly regardless gender, among them, men elderly show extreme tendency concentrated on modern korean long series novel. In the correlation analysis, the male elderly showed a weak negative correlation with the adult male of r = -0.222, and the negative direction of all the other groups showed that the tendency of male elderly's loan book was opposite.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.12 no.2
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• pp.21-34
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• 2002

In this paper we propos a new hardware architecture of modular exponentiation using a division chain method which has been proposed in (2). Modular exponentiation using the division chain is performed by receding an exponent E as a mixed form of multiplication and addition with divisors d=2 or $d=2^I +1$ and respective remainders r. This calculates the modular exponentiation in about $1.4log_2$E multiplications on average which is much less iterations than $2log_2$E of conventional Binary Method. We designed a linear systolic array multiplier with pipelining and used a horizontal projection on its data dependence graph. So, for k-bit key, two k-bit data frames can be inputted simultaneously and two modular multipliers, each consisting of k/2+3 PE(Processing Element)s, can operate in parallel to accomplish 100% throughput. We propose a new encoding scheme to represent divisors and remainders of the division chain to keep regularity of the data path. When it is synthesized to ASIC using Samsung 0.5 um CMOS standard cell library, the critical path delay is 4.24ns, and resulting performance is estimated to be abort 140 Kbps for a 1024-bit data frame at 200Mhz clock In decryption process, the speed can be enhanced to 560kbps by using CRT(Chinese Remainder Theorem). Futhermore, to satisfy real time requirements we can choose small public exponent E, such as 3,17 or $2^{16} +1$, in encryption and verification process. in which case the performance can reach 7.3Mbps.