• 제목/요약/키워드: Parallel Process

검색결과 1,456건 처리시간 0.026초

병렬 처리를 이용한 용접 공정 유한 요소 해석 (Finite element analysis of welding process by parallel computation)

  • 임세영;김주완;최강혁;임재혁
    • 대한용접접합학회:학술대회논문집
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    • 대한용접접합학회 2003년도 추계학술발표대회 개요집
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    • pp.156-158
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    • 2003
  • An implicit finite element implementation for Leblond's transformation plasticity constitutive equations, which are widely used in welded steel structure is proposed in the framework of parallel computing. The implementation is based upon the multiplicative decomposition of deformation gradient and hyper elastic formulation. We examine the efficiency of parallel computation for the finite element analysis of a welded structure using domain-wise multi-frontal solver.

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트랜스퓨터를 사용한 피라미드형 병렬 어레이 컴퓨터 (TPPAC) 구조 (Transputer-based Pyramidal Parallel Array Computer(TPPAC) architecture (Prelimineary Version))

  • 정창성;정철환
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1988년도 전기.전자공학 학술대회 논문집
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    • pp.647-650
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    • 1988
  • This paper proposes and sketches out a new parallel architecture of transputer-based pyramidal parallel array computer (TPPAC) used to process computationally intensive problems for geometric processing applications such as computer vision, image processing etc. It explores how efficiently the pyramid computer architecture is designed using transputer chips, and poses a new interconnection scheme for TPPAC without using additional transputers.

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High Speed Parallel Fault Detection Design for SRAM on Display Panel

  • Jeong, Kyu-Ho;You, Jae-Hee
    • 한국정보디스플레이학회:학술대회논문집
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    • 한국정보디스플레이학회 2007년도 7th International Meeting on Information Display 제7권1호
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    • pp.806-809
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    • 2007
  • SRAM cell array and peripheral circuits on display panel are designed using LTPS process. To overcome low yield of SOP, high speed parallel fault detection circuitry for memory cells is designed at local I/O lines with minimal overhead for efficient memory cell redundancy replacement. Normal read/write and parallel test read/write are simulated and verified.

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The Mapping Method for Parallel Processing of SAR Data

  • In-Pyo Hong;Jae-Woo Joo;Han-Kyu Park
    • 한국통신학회논문지
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    • 제26권11A호
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    • pp.1963-1970
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    • 2001
  • It is essential design process to analyze processing method and set out top level HW configuration using main parameters before implementation of the SAR processor. This paper identifies the impact of the I/O and algorithm structure upon the parallel processing to be assessed and suggests the practical mapping method fur parallel processing to the SAR data. Also, simulation is performed to the E-SAR processor to examine the usefulness of the method, and the results are analyzed and discussed.

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실험계획법을 이용한 3 자유도 마이크로 병렬기구 플랫폼의 제어 이득 선정 (Control Gain Tuning of the 3-DOF Micro Parallel Mechanism Platform Via Design of Experiment Methodology)

  • 서태원
    • 한국정밀공학회지
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    • 제29권11호
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    • pp.1207-1213
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    • 2012
  • Typically commercial controllers do not give data of the controller gains. Therefore, it is very hard to determine the optimal controller gain even though the dynamic model is derived. In this case, design of experiment (DOE) methodology can be a powerful tool for gain tuning. In this research, gain tuning process is proposed based on the DOE. Micro parallel mechanism platform with 3 degrees-of-freedom (DOF) is used for the experiments. Controller gains are measured indirectly from the voltages of adjustable resistors. The controller gains of three actuators are optimized by two or three steps, respectively. The correlations of the controller gains are also analyzed. The process and methodology can be adopted in gain tuning of other mechanical systems.

파일 및 병렬 처리를 이용한 표면 객체의 복셀화 방안 (The Voxelization of Surface Objects using File handling and Parallel Processing)

  • 이수열;안은영
    • 한국멀티미디어학회논문지
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    • 제18권2호
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    • pp.113-119
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    • 2015
  • This paper suggests an efficient method for making the high resolution volexlized model from a polygonal surface object. A distinctive strength of the method is that a surface model, however complex one, can be transformed and formed an absolute voxelized solid model in a various resolution. It caused by producing a voxel by integrating the informations for the candidated voxels separately detected in each 3D-axial direction. This method reduces memory complexity by storing the information of voxels that is produced during the 2-phase volxelization(surface and inner voxelization) of a surface object in a binary file. For the computational efficiency, a parallel process using multi-threads is applied in the process of the inner voxelization, it also takes advantage of time complexity.

Full Search Equivalent Motion Estimation Algorithm for General-Purpose Multi-Core Architectures

  • Park, Chun-Su
    • 반도체디스플레이기술학회지
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    • 제12권3호
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    • pp.13-18
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    • 2013
  • Motion estimation is a key technique of modern video processing that significantly improves the coding efficiency significantly by exploiting the temporal redundancy between successive frames. Thread-level parallelism is a promising method to accelerate the motion estimation process for multithreading general-purpose processors. In this paper, we propose a parallel motion estimation algorithm which parallelizes the motion search process of the current H.264/AVC encoder. The proposed algorithm is implemented using the OpenMP application programming interface (API) and can be easily integrated into the current encoder. The experimental results show that the proposed parallel algorithm can reduce the processing time of the motion estimation up to 65.08% without any penalty in the rate-distortion (RD) performance.

불확실 동적 환경에서 다각형 부품의 평행-턱 파지 계획 (Parallel-Jaw Grasp Planning of Polygonal Parts in Uncertain Dynamic Environments)

  • 한인환;조정호
    • 한국정밀공학회지
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    • 제14권4호
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    • pp.126-135
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    • 1997
  • A sensorless motion planner which succeeds in grasping a polygonal part firmly into a desired orientation has been developed through the dynamic analysis. The analytical results on the impact process with friction are used for modeling the contact motionduring the parallel-jaw grasp operation, which is com- posed of the pushing and the squeezing process. The developed planner succeeds in grasping a part into a specified orientation in the face of uncertainties of initial position and orientation of the part, motion direction of the finger, and the physical parameters such as the coefficients of friction and restitution. The motion planner has been fully implemented into a viable package on the computer system, and verified experimentally. The motion of parts is recorded using a high-speed video camera, and then compared to the results of the planner and the graphic simulation results that illustrate the simulated motion of the grasp operation.

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An adaption algorithm for parallel model reference bilinear systems

  • Yeo, Yeong-Koo;Song, Hyung-Keun
    • 제어로봇시스템학회:학술대회논문집
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    • 제어로봇시스템학회 1987년도 한국자동제어학술회의논문집(한일합동학술편); 한국과학기술대학, 충남; 16-17 Oct. 1987
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    • pp.721-723
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    • 1987
  • An Adaptation algorithm is presented and a convergence criterion is derived for parallel model reference adaptive bilinear systems. The output error converges asymptotically to zero, and the parameter estimates are bounded for stable reference models. The convergence criterion depends only upon the input sequence and a priori estimates of the maximum parameter values.

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Disjunctive Process Patterns Refinement and Probability Extraction from Workflow Logs

  • Kim, Kyoungsook;Ham, Seonghun;Ahn, Hyun;Kim, Kwanghoon Pio
    • 인터넷정보학회논문지
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    • 제20권3호
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    • pp.85-92
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    • 2019
  • In this paper, we extract the quantitative relation data of activities from the workflow event log file recorded in the XES standard format and connect them to rediscover the workflow process model. Extract the workflow process patterns and proportions with the rediscovered model. There are four types of control-flow elements that should be used to extract workflow process patterns and portions with log files: linear (sequential) routing, disjunctive (selective) routing, conjunctive (parallel) routing, and iterative routing patterns. In this paper, we focus on four of the factors, disjunctive routing, and conjunctive path. A framework implemented by the authors' research group extracts and arranges the activity data from the log and converts the iteration of duplicate relationships into a quantitative value. Also, for accurate analysis, a parallel process is recorded in the log file based on execution time, and algorithms for finding and eliminating information distortion are designed and implemented. With these refined data, we rediscover the workflow process model following the relationship between the activities. This series of experiments are conducted using the Large Bank Transaction Process Model provided by 4TU and visualizes the experiment process and results.