• 대한전자공학회논문지SD
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• 제48권1호
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• pp.39-49
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• 2011

터보 코드는 반복 복호를 하기 때문에 긴 복호시간을 필요로 한다. 고속 통신을 하기 위해서는 복호 시간을 줄여야 하며 이는 병렬 처리를 통해 해결할 수 있다. 하지만 병렬 처리 시 메모리 경합이 발생할 수 있는데 이는 복호기의 성능을 저하시킨다. 이러한 메모리 정합을 피하기 위해 2006년 QPP 인터리버가 제안되었다. 본 논문에서는 QPP 인터리버에 적합하며 비교적 적은 지연 시간을 갖고 회로의 크기도 줄인 MDF 기법을 제안한다. 그리고 MDF 기법을 사용한 MAP 복호 모듈의 설계를 보인다. 구현한 복호기는 Xilinx 사의 FPGA에 타켓팅하였으며 최대 80Mbps의 처리율을 보인다.

• Journal of Information Processing Systems
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• 제6권4호
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• pp.537-552
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• 2010

Software Debugging is the most time consuming and costly process in the software development process. Many techniques have been proposed to isolate different faults in a program thereby creating separate sets of failing program statements. Debugging in parallel is a technique which proposes distribution of a single faulty program segment into many fault focused program slices to be debugged simultaneously by multiple debuggers. In this paper we propose a new technique called Faulty Slice Distribution (FSD) to make parallel debugging more efficient by measuring the time and labor associated with a slice. Using this measure we then distribute these faulty slices evenly among debuggers. For this we propose an algorithm that estimates an optimized group of faulty slices using as a parameter the priority assigned to each slice as computed by value of their complexity. This helps in the efficient merging of two or more slices for distribution among debuggers so that debugging can be performed in parallel. To validate the effectiveness of this proposed technique we explain the process using example.

• 한국컴퓨터정보학회논문지
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• 제18권1호
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• pp.1-10
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• 2013

본 논문은3차원레이저레이더(LADAR, Laser Ladar) 영상 생성 시스템 개발을 수행함에 있어, 요구되는 실시간 처리를 구현하기 위해 CPU(Central Processing Unit) 및 GPU(Graphic Processing Unit)의 병렬처리 구조를 설계하는 CUDA(Common Unified Device Architecture) 기반 소프트웨어(SW, Software) 구현 기법에 대하여 설명한다. LADAR 시스템은 레이저 거리정보를 기반으로 3차원 영상을 생성하는 복잡도 높은 시스템으로써, 각 단계별로 많은 량의 처리 자원이 필요하다. 따라서, 한정된 시스템 자원 내에서 이를 실시간으로 처리하기 위해서는 반드시 병렬처리 구조를 설계 및 적용해야 한다. 본 논문에서는, 처리 알고리즘의 단계적 분석을 통해 분할 가능한 작업에 대하여 CUDA GPU로 할당 및 처리를 수행함으로써, 시스템에서 요구하는 실시간 처리를 달성하였으며, 처리 속도 분석을 통해 최대 46%의 처리 속도 향상을 확인할 수 있었다.

• Management Science and Financial Engineering
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• 제13권2호
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• pp.47-77
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• 2007

This paper considers a scheduling problem where a customer orders multiple products(jobs) from a production facility. The objective is to minimize the sum of the order(batch) completion times. While a machine can process only one job at a time, multiple machines can simultaneously process jobs in a batch. Although each job has a unique processing time, we consider the case where batch processing times are identical. This simplification allows us to develop heuristics with improved performance bounds. This problem was motivated by a real world problem encountered by foreign electronics manufacturers. We first establish the complexity of the problem. For the two parallel machine case, we introduce two simple but intuitive heuristics, and find their worst case relative error bounds. One bound is tight and the other bound goes to 1 as the number of orders goes to infinity. However, neither heuristic is superior for all instances. We extend one of the heuristics to an arbitrary number of parallel machines. For a fixed number of parallel machines, we find a worst case bound which goes to 1 as the number of orders goes to infinity. Then, a tighter bound is found for the three parallel machine case. Finally, the heuristics are empirically evaluated.

• 대한전자공학회논문지SD
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• 제47권5호
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• pp.41-47
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• 2010

본 논문에서는 SSD (solid state disk)에 쓰이는 NAND flash 메모리 에러 정정에 관한 오류정정 방법 중에서 Parallel BCH(Bose-Chaudhuri-Hocquenghem) 방법 및 VLSI 설계를 제안하였다. 제안된 설계는 에러 정정 능력(t=18, 8) 을 가변적으로 하여 사용빈도수의 증가로 높은 에러 율을 가진 데이터 공간에 신뢰성을 높였고, 디코더의 병렬처리 비트 수를 인코더의 처리 비트 수에 2배로 하여 디코더의 수행시간을 줄였고 이에 따르는 latency도 기존 회로에 비해 1/2로 감소함을 확인 하였다.

• 한국기계가공학회지
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• 제20권6호
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• pp.82-91
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• 2021

We compared the heat transfer characteristics of the parallel and the counterflow flow in the concentric double tube of the Al₂O₃/water nanofluids using numerical methods. The high- and low-temperature fluids flow through the inner circular tube and the annular tube, respectively. The heat transfer characteristics according to the flow direction were compared by changing the volume flow rate and the volume concentration of the nanoparticles. The results showed that the heat transfer rate and overall heat transfer coefficient improved compared to those of basic fluid with increasing the volume and flow rate of nanoparticles. When the inflow rate was small, the heat transfer performance of the counterflow was about 22% better than the parallel flow. As the inflow rate was increased, the parallel flow and the counterflow had similar heat transfer rates. In addition, the effectiveness of the counterflow increased from 10% to 22% rather than the parallel flow. However, we verified that the increment in the friction factor of the counterflow is not large compared to the increment in the heat transfer rate.

• 한국시뮬레이션학회논문지
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• 제8권2호
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• pp.57-72
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• 1999

With the rapidly increasing complexity of decision-marking or system development in the fields of industry, management, etc., modelling techniques using simulation has become more highlighted. Particularly, the advent of parallel computer systems not only has opened a new horizon of parallel simulation, but also has greatly contributed to the speed-up of the execution of simulation. The implementation of parallel simulation, however, is not a easy job for those who accustomed to the existing computer systems. And it is also necessarily confronted with the problem of synchronization conflict in the process. Thus, how to allow a wider community of users to gain access to parallel simulation while solving synchronization conflicts has become an important issue in simulation study. As a method to solve these problems, this paper is primarily concerned with the implementation of GPSS which is a generally used simulation language for discrete event simulation, onto a parallel computer using C-LINDA. For that, this paper, is to suggest a model and algorithm and to experiment it using a case.

• 한국철도학회:학술대회논문집
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• 한국철도학회 2004년도 추계학술대회 논문집
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• pp.1235-1240
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• 2004

This paper has presented the parallel cyclic redundancy check (CRC) technique that performs CRC computation in parallel superior to the conventional CRC technique that processes data bits serially. Also, it has showed that the implemented parallel CRC circuit had been successfully applied to the inductively coupled passive RFID system working at a frequency of 13.56MHz in order to process the detection of logical faults more fast and the system had been verified experimentally. In comparison with previous works, the proposed RFID system using the parallel CRC technique has been shown to reduce the latency and increase the data processing rates in the results. Therefore, it seems reasonable to conclude that the parallel CRC realization in the RFID system offers a means of maintaining the integrity of data in the high speed RFID system.

• 제어로봇시스템학회논문지
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• 제15권5호
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• pp.488-495
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• 2009

This paper presents a fast feature extraction method for autonomous mobile robots utilizing parallel processing and based on OpenMP, SSE (Streaming SIMD Extension) and CUDA programming. In the first step on CPU version, the algorithms and codes are optimized and then implemented by parallel processing. The parallel algorithms are debugged to maintain the same level of performance and the process for extracting key points and obtaining dominant orientation with respect to key points is parallelized. After extraction, a parallel descriptor via SSE instructions is constructed. And the GPU version also implemented by parallel processing using CUDA based on the SIFT. The GPU-Parallel descriptor achieves an acceleration up to five times compared with the CPU-Parallel descriptor, but it shows the lower performance than CPU version. CPU version also speed-up the four and half times compared with the original SIFT while maintaining robust performance.

• 정보처리학회논문지:컴퓨터 및 통신 시스템
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• 제11권6호
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• pp.167-174
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• 2022

PIPO 경량 블록암호는 ICISC'20에서 발표된 암호이다. 본 논문에서는 32-bit RISC-V 프로세서 상에서 PIPO 경량 블록암호 ECB, CBC, CTR 운용 모드의 단일 블록 최적화 구현과 병렬 최적화 구현을 진행한다. 단일 블록 구현에서는 32-bit 레지스터 상에서 효율적인 8-bit 단위의 Rlayer 함수 구현을 제안한다. 병렬 구현에서는 병렬 구현을 위한 레지스터 내부 정렬을 진행하며, 서로 다른 4개의 블록이 하나의 레지스터 상에서 Rlayer 함수 연산을 진행하기 위한 방법에 대해 설명한다. 또한 CBC 운용모드의 병렬 구현에서는 암호화 과정에 병렬 구현 기법 적용이 어렵기 때문에 복호화 과정에서의 병렬 구현 기법 적용을 제안하며, CTR 운용모드의 병렬 구현에서는 확장된 초기화 벡터를 사용하여 레지스터 내부 정렬 생략 기법을 제안한다. 본 논문에서는 병렬 구현 기법이 여러 블록암호 운용모드에 적용 가능함을 보여준다. 결과적으로 ECB 운용모드에서 키 스케줄 과정을 포함하고 있는 기존 연구 구현의 성능 대비 단일 블록 구현에서는 1.7배, 병렬 구현에서는 1.89배의 성능 향상을 확인하였다.