• Journal of Computational Design and Engineering
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• v.2 no.3
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• pp.148-156
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• 2015

Increased competitive challenges are forcing companies to find better ways to bring their applications to market faster. Distributed development environments can help companies improve their time-to-market by enabling parallel activities. Although, such environments still have their limitations in real-time communication and real-time collaboration during the product development process. This paper describes a web-based collaborative framework which has been developed to support the decision making on a 3D design developing process. The paper describes 3D design file for the discussion that contains all relevant annotations on its surface and their visualization on the user interface for design changing. The framework includes a native CAD data converting module, 3D data based real-time communication module, revision control module for 3D data and some sub-modules such as data storage and data management. We also discuss some raised issues in the project and the steps underway to address them.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.6
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• pp.88-97
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• 1994

We describe the design, fabrication, and performance of the optical fiber-photodiode 1$\times$12 arry module using mesa-type InS10.53T GaS10.47TAS/INP 1$\times$12 PIN photodiode array. We fabricated the PIN PD array for high-speed optical fiber parallel data link optimizing quantum efficiency, operating speed sensitivity from the PIN-FET structure, and electrical AC crosstalk. For each element of the array, the diameter of the photodetective area is 80 $\mu$m, the diameter of the p-metal pad is 90 $\mu$m, and the photodiode seperation is 250 $\mu$m to use Si v-groove. Ground conductor line is placed around diodes and p-metal pads are formed in zigzag to reduce Ac capacitance coupling between array elements. The dark current (IS1dT) is I nA and the capacitance(CS1pDT) is 0.9 pF at -5 V. No signifcant variations of IS1dT and CPD from element to element in the array were observed. We calulated the coupling efficiency for 10/125 SMF and 50/125 GI MMF, and measured the responsivity of the PD array at the wavelength is 1.55 $\mu$ m. Responsivities are 0.93 A/W for SMF and 0.96 A/W for MMF. The optical fiber-PD array module is useful in numerous high speed digital and analog photonic system applications.

• Proceedings of the KIEE Conference
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• 2000.07c
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• pp.1614-1616
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• 2000

The purpose of this study is to manufacture and test a thermoelectric generator which converts unused energy from close-at-hand sources, such as garbage incineration heat and industrial exhaust, to electricity. A manufacturing process and the properties of a thermoelectric generator are discussed before simulating the thermal stress and thermal properties of a thermoelectric module located between an aluminum tube and alumina plate. We can design the thermoelectric modules having the good properties of thermoelectric generation. Resistivity of thermoelectric module for thermoelectric generation consisting of 62 cells was $0.15{\sim}0.4{\Omega}$. The maximum power of thermoelectric generator using thermoelectric generating modules can be defined as temperature function, and in this case it can be analogized the linear relation between current and voltage characteristics as function of temperature. The thermoelectric generator using 128 generating modules was assembled with 4 parallel connected modules sets composed with 32 directly connected modules.

• The Transactions of the Korean Institute of Power Electronics
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• v.12 no.2
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• pp.165-173
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• 2007

This paper introduces a new current sharing technique to Interleaved Boost Converter (IBC) using carrier slope control. The IBC is able to boost the input voltage and operates at higher current levels and has various advantages over a single power module. However, how to balance the current each module is still important problem. To solve this problem, the proposed technique can distribute the power and load current equally based on master-slave current sharing method. Unlike a conventional approach, this technique can be extended even though the current stress of switching components at slave modules is significantly smaller than that of the master module. The simulation and the experimental results are presented to show the validity.

• Journal of Power Electronics
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• v.15 no.6
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• pp.1429-1437
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• 2015

A new parallel hybrid soft switching converter with low circulating current losses during the freewheeling state and a low output current ripple is presented in this paper. Two circuit modules are connected in parallel using the interleaved pulse-width modulation scheme to provide more power to the output load and to reduce the output current ripple. Each circuit module includes a three-level converter and a half-bridge converter sharing the same lagging-leg switches. A resonant capacitor is adopted on the primary side of the three-level converter to reduce the circulating current to zero in the freewheeling state. Thus, the high circulating current loss in conventional three-level converters is alleviated. A half-bridge converter is adopted to extend the ZVS range. Therefore, the lagging-leg switches can be turned on under zero voltage switching from light load to full load conditions. The secondary windings of the two converters are connected in series so that the rectified voltage is positive instead of zero during the freewheeling interval. Hence, the output inductance of the three-level converter can be reduced. The circuit configuration, operation principles and circuit characteristics are presented in detail. Experiments based on a 1920W prototype are provided to verify the effectiveness of the proposed converter.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.1
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• pp.110-119
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• 2017

This paper describes a CMOS image sensor (CIS) with dual correlated double sampling (CDS) and column-parallel analog-to-digital converter (ADC) and its measurement method using a field-programmable gate array (FPGA) integrated module. The CIS is composed of a $320{\times}240$ pixel array with $3.2{\mu}m{\times}3.2{\mu}m$ pixels and column-parallel 10-bit single-slope ADCs. It is fabricated in a $0.11-{\mu}m$ CIS process, and consumes 49.2 mW from 1.5 V and 3.3 V power supplies while operating at 6.25 MHz. The measured dynamic range is 53.72 dB, and the total and column fixed pattern noise in a dark condition are 0.10% and 0.029%. The maximum integral nonlinearity and the differential nonlinearity of the ADC are +1.15 / -1.74 LSB and +0.63 / -0.56 LSB, respectively.

• 한국초전도학회:학술대회논문집
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• v.10
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• pp.272-275
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• 2000

We investigated a resistive superconducting fault current limiter (SFCL) fabricated using YBCO thin films on 2-inch diameter sapphire substrates. Nearly identical SFCL units were prepared and tested. The units were connected in series and parallel to increase the current and voltage ratings. A serial connection of the units showed significantly unbalanced power dissipation between the units. This imbalance was removed by introducing a shunt resistor to the firstly quenched unit. Parallel connection of the units increased the current rating. An SFCL module of 4 units in parallel, each of which has minimum quench current 25 Ap, was produced and successfully tested at a 220 V circuit. From the resistance increase, we estimated that the film temperature increases to 200 K in 5 msec, and 300 K in 120 msec. Successive quenches revealed that this system is stable without degradation in the current limiting capability under such thermal shocks as quenches at 220 V.

• Journal of the Korean Solar Energy Society
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• v.29 no.2
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• pp.8-13
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• 2009

In this paper, two configurations of PV array are analyzed and tested under shading condition, where two configurations are series-parallel and total-crass-tied configuration. Each photovoltaic module is emulated by two 5 inch po1y-crystalline cells in series and an array is constructed by connecting 24 of the modules to compare a generated maximum power of the two configurations. Pspice and Sun simulator. PASAN IIIb, are used for simulation and experiment to test the array under various partial shading conditions. Test results show the total-cross-tied configuration generates 7.63% higher maximum power than the series-parallel configuration, and it is well matched to the analysis and simulations of the two configurations.

• The Journal of the Korea institute of electronic communication sciences
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• v.14 no.1
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• pp.81-86
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• 2019

This paper is concerned with a system design that enables a the plurality of switching mode power supplies to be supplied with larger power through a parallel connection. For this purpose, a shunt resistor is placed in series at the output of the constant voltage regulator and the output voltage is sensed and controlled using an arduino. In this paper, two constant-voltage regulators were used for the experiment, but it is possible to generalize for more boards. By using the method that controls the system, the sum of the currents delivered by the two systems to the load was found to be 96% of the current drawn from each board. In case of efficiency, 92.4% efficiency is achieved in the unit board and the efficiency in parallel connection is about 90%.

• The Transactions of the Korean Institute of Power Electronics
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• v.27 no.5
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• pp.367-375
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• 2022

Generally, a proportional-resonant controller is used to eliminate steady-state errors during the voltage-current control of a double-conversion uninterruptible power supply (UPS) in a stationary reference frame. Additionally, the feed-forward control compensating for the load current, which can be considered a disturbance of the voltage controller, can be used to improve the disturbance rejection performance. However, during the parallel operation of UPSs, circulating current can occur between UPS modules when performing both feed-forward control and droop control because feed-forward control reduces the circulating current impedance. This study proposes a feed-forward compensation technique that considers the impedance of circulating current. An additional feed-forward compensation technique is developed to enhance the disturbance rejection performance. The validity of the proposed feed-forward compensation technique is verified by the experiment results of the parallel operation of a 500 W double-conversion UPS module.