• KSII Transactions on Internet and Information Systems (TIIS)
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• v.11 no.3
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• pp.1684-1699
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• 2017

The deblocking filter (DF) reduces blocking artifacts in encoded video sequences, and thereby significantly improves the subjective and objective quality of videos. Statistics show that the DF accounts for 5-18% of the total decoding time in high-efficiency video coding. Therefore, speeding up the DF will improve codec performance, especially for the decoder. In view of the rapid development of multicore technology, we propose a parallel DF scheme based on a modified order of accessing the coding tree units (CTUs) by analyzing the data dependencies between adjacent CTUs. This enables the DF to run in parallel, providing accelerated performance and more flexibility in the degree of parallelism, as well as finer parallel granularity. We additionally solve the problems of variable privatization and thread synchronization in the parallelization of the DF. Finally, the DF module is parallelized based on the HM16.1 reference software using OpenMP technology. The acceleration performance is experimentally tested under various numbers of cores, and the results show that the proposed scheme is very effective at speeding up the DF.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.1
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• pp.86-92
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• 2009

This paper presents development of 6kw ZVS(Zero Voltage Switching) boost converter by 4-parallel operation. To realize a high capacity converter with 6 kw, 4-parallel operation of 1.5kW unit module is proposed in this paper. To meet high ratio input to output voltage, isolated type booster converter is designed. To achieve ZVS operation of 4-switches of full bridge and protect a voltage overshoot caused by switch turn-off, simple active-clamp circuit is applied to the primary side. For parallel operation of 4-modules, master-slave control method is proposed to achieve input current sharing of 4-unit converter modules accurately. For performance tests, simulation is carried out. Also, load and experimental tests of the developed booster converter, 230Vdc/6kW, are carried out under various conditions. For field tests, the developed converter is applied for boosting a battery power to high DC_link voltage for a VSI inverter which starts a micro-turbine(MT) installed in vehicle and it's performance is verified through high speed motoring a MT up to tens of thousands of rpm.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1029-1032
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• 1998

In this paper, a comparative study is presented to evaluate the addition architecture of the high-speed checksum module in TCP/IP processing. In order to speed up TCP/IP processing, H/W implementation offers concurrent and parallel processing to yield high speed computation, with respect to S/W implementation. This research aims at comparing two addition architectures of checksum module, which is the major botteleneck in TCP/IP processing. The 16-bit and 8-bit byte-by-byte addition architecture are implemented by the full custom design, and compared, in analytical and experimental manner, from standpoint of space and performance. For LG $0.6\mu\textrm{m}$ TLM process, the 8-bit addition implementation requires the area, 1.3 times larger than the 16-bit one, and it operates at 80MHz while the 16-bit one runs by 66MHz.

• Journal of the Korean Society of Industry Convergence
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• v.7 no.2
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• pp.207-213
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• 2004

This paper describes the development of Behind-Tape-Reader (BTR) type DNC system using CYBER 180-830 as a central computer and IBM PC-AT cell control computer and NC lathe with FANUC 5T NC controller. In this system, the connection between central computer and cell control computer is done via RS-232C serial interface board, and that between cell control computer and FANUC 5T controller is done via parallel interface board. The software consists of two module, central computer communication module for NC program downloading and status uploading, NC machine running module for NC operating.

• ETRI Journal
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• v.28 no.5
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• pp.648-651
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• 2006

In this letter we present a right-angle-bent coplanar waveguide (CPW) which we developed for the application of the driver amplifier-integrated (DAI) 40 Gbps traveling wave electroabsorption modulated laser module. The developed CPW realized parallel progression of the radio frequency (RF) and light using a dielectric overlay structure and wedge bonding on the bending section. The measured $S_{11}$ and $S_{21}$ of the developed CPW were kept below-10 dB up to 35 GHz and -3 dB up to 43 GHz, respectively. These measured results of the CPW were in good agreement with the simulation results and demonstrated the applicability of the CPW to the 40 Gbps communication module.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.25 no.11
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• pp.83-90
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• 2011

There are two main types of concentrating optical systems in use today: refractive types that use Fresnel lenses, and reflective systems that use one or more mirrors. Regardless of the chosen optical system, the result is concentrated sunlight being aimed at the sensitive face of the cell, to produce more energy from less photovoltaic material. In this paper, for the achieve trackerless CPV system, CPV module included that the spherical lens with reflect mirror makes it possible to achieve high and stable power generation performance for the high concentration photovoltaic power generation system and cope with the needs for a variety of shapes and sizes in flexible manners and that the multiple cavity assemble method greatly reduces costs. Development of these high performance multi-junction CPV module promises to accelerate growth in photovoltaic power generation.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.29B no.10
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• pp.10-18
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• 1992

This paper considers and implementation of the memory system which provides simultaneous access to pq image points of block(p$\times$q), horizontal vector(1$\times$pq)and/vertical vector(pq$\times$1) in 2-dimension image array, where p and q are design parameters. This memory system consists of an address calculation circuit, address routing circuit, data routing circuit, module selection circuit and m memory modules where m>qp. The address calculation circuit computes pq addresses in parallel by using the difference of addresses among image points. Extra module assignment circuit is not used by improving module selection circuit with routhing circuit. By using Verilog-XL logic simulator, we verify the correctness of the memory system and estimate the performance. The implemented system provides simultaneous access to 16 image points and is 6 times faster than conventional memory system.

• Proceedings of the Korea Information Processing Society Conference
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• 2015.04a
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• pp.934-937
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• 2015

본 논문은 비디오 디코더의 병목현장을 해결하고 대량의 데이터를 처리할 수 있는 다중병렬처리방식의 HEVC CABAC 디코더를 소개한다. CABAC 디코더를 병렬화한 하드웨어 VLSI구조를 설계하여 크기 대비 높은 처리량이 나오는지를 설계 및 분석결과를 통해 연구결과를 도출하는 게 본 논문의 목적이다. CABAC 디코더 내부 module(산술 디코더, 문맥 모델러, 역이진화기) 1개에서 4개까지의 병렬화를 분석한 결과 4개의 병렬화를 했을 때가 크기 대비 처리량이 가장 높다는 것을 알 수 있었다. 또한 내부 module 4개를 병렬화한 CABAC 디코더 4개를 병렬화하여 slice 단위로 나눠진 프레임 1개를 한 번에 처리하는 방식을 채택하였다. 본 논문에서는 각 CABAC 디코더의 내부 module 4개를 병렬화하고, 병렬화한 CABAC 디코더 4개를 다시 병렬화하는 하드웨어 구조를 사용한다.

• Membrane and Water Treatment
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• v.4 no.3
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• pp.191-202
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• 2013

The application of ultrafiltration operation to the dialysis in countercurrently parallel-flow rectangular membrane modules was investigated. The assumption of uniform ultrafiltration flux was made for operation with slight concentration polarization and declination of transmembrane pressure. Considerable improvement in mass transfer is achievable if the operation of ultrafiltration is applied, especially for the system with low mass transfer coefficient. The enhancement in separation efficiency is significantly increased with increasing ultrafiltration flux, as well as with increasing the volumetric flow rates. Furthermore, increasing the volumetric flow rate in retentate phase is more beneficial to mass transfer than increasing in dialysate phase.

• Proceedings of the KIEE Conference
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• 1998.11b
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• pp.575-578
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• 1998

In this paper, we propose a VLSI architecture of Reed-Solomon decoder. Our goal is the development of an architecture featuring parallel and pipelined processing to improve the speed and low power design. To achieve the this goal, we analyze the RS decoding algorithm to be used parallel and pipelined processing efficiently, and modified the Euclid's algorithm arithmetic part to apply the parallel structure in RS decoder. The overall RS decoder are compared to Shao's, and we show the 10% area efficiency than Shao's time domain decoder and three times faster, in addition, we approve the proposed RS decoders with Altera FPGA Flex 10K-50, and Implemeted with LG 0.6{\mu}$ processing.