• Title/Summary/Keyword: Parallel Implementation

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High Performance Coprocessor Architecture for Real-Time Dense Disparity Map (실시간 Dense Disparity Map 추출을 위한 고성능 가속기 구조 설계)

  • Kim, Cheong-Ghil;Srini, Vason P.;Kim, Shin-Dug
    • The KIPS Transactions:PartA
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    • v.14A no.5
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    • pp.301-308
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    • 2007
  • This paper proposes high performance coprocessor architecture for real time dense disparity computation based on a phase-based binocular stereo matching technique called local weighted phase-correlation(LWPC). The algorithm combines the robustness of wavelet based phase difference methods and the basic control strategy of phase correlation methods, which consists of 4 stages. For parallel and efficient hardware implementation, the proposed architecture employs SIMD(Single Instruction Multiple Data Stream) architecture for each functional stage and all stages work on pipelined mode. Such that the newly devised pipelined linear array processor is optimized for the case of row-column image processing eliminating the need for transposed memory while preserving generality and high throughput. The proposed architecture is implemented with Xilinx HDL tool and the required hardware resources are calculated in terms of look up tables, flip flops, slices, and the amount of memory. The result shows the possibility that the proposed architecture can be integrated into one chip while maintaining the processing speed at video rate.

A Study on the Method for Promoting Acceptance on Performance Management : Focusing on the Public Enterprises Practices (성과관리의 수용성 제고 방안 : 공기업사례를 중심으로)

  • Kim, Youn Sung;Yoo, Hong Sung;Kim, Sun Cheol
    • Journal of the Korean Operations Research and Management Science Society
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    • v.40 no.1
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    • pp.185-198
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    • 2015
  • This study drew performance management factors analyzed a causal link between acceptance and satisfaction of performance management to present the method for promoting acceptance on the performance management system that most of the public enterprises, government-affiliated organizations are implementing. To achieve this, qualitative analysis and quantitative analysis were conducted in parallel through in-depth case studies and surveys. The results of this study are as follows. First, the analysis of the performance management factors with preceding studies shows that performance management indicators, performance management operations and performance management communications. Second, from the causal relationship of performance management factors affecting performance management acceptance reveals that performance management operation has statistical significance. Third, the analysis of the effect of performance management factors on the management satisfaction shows that operation and indicator of the performance management have statistical significance and reflecting the performance indicators to business, adequacy of target level, training, system support and CEO's Leadership have been revealed as important variables to the management satisfaction. Fourth, the result of the analysis on casual connection between acceptance and satisfaction of the performance management shows that improving management acceptance has a direct impact on satisfaction because performance management receptiveness were deemed statistically significant. Fifth, the result of the in-depth case studies on improving performance management acceptance shows that public enterprises have been putting in an effort to design indicators and try to encourage internal member's involvement during the monitoring and evaluation. The quantitative analysis based on survey has turned out that performance management operation and performance management indicators have statistical significance. The qualitative analysis by in-depth analysis shows that public enterprises put a lot of effort to performance management indicators and communication between internal members. As a result, commitment to performance management operation is required to improve the performance management acceptance. In other words, a detailed implementation plan for training, information system support, and CEO's leadership has to be established and ought to be pushed.

An Implementation of Spatio-Temporal Graph to Represent Situations in the Virtual World (가상현실 속의 상황 표현을 위한 시공간 그래프의 구현)

  • Park, Jong-Hee;Jung, Gung-Hun
    • The Journal of the Korea Contents Association
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    • v.13 no.6
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    • pp.9-19
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    • 2013
  • In this paper, we develop a Spatio-Temporal graph as of a key component of our knowledge representation Scheme. We design an integrated representation scheme to depict not only present and past but future in parallel with the spaces in an effective and intuitive manner. An event in general occupies not only a space but a time. Hence a crucial premise for the simulation of virtual situations is to position events in the multi-dimensional context, that is, 3-D space extended by the temporal dimension. Furthermore an event tends to have physical, social and mental aspects intertwined. As a result we need diverse information structures and functions to model entities and relations associated with events and to describe situations in different stances or perspectives of the virtual agents. These structures and functions are implemented in terms of integrated and intuitive representation schemes at different levels such as Ontology View, Instance View, ST View, Reality View. The resulting multi-dimensional comprehensive knowledge structure accommodates multi-layered virtual world developing in the time to maximize the diversity of situations in the historical context. The viability of this knowledge representation scheme is demonstrated with a typical scenario applied to a simulator implemented based on the ST Graph. The virtual stage based on the ST graph can be used to provide natural contexts for situated learning or next-generation simulation games.

A Comparative Performance Analysis of Spark-Based Distributed Deep-Learning Frameworks (스파크 기반 딥 러닝 분산 프레임워크 성능 비교 분석)

  • Jang, Jaehee;Park, Jaehong;Kim, Hanjoo;Yoon, Sungroh
    • KIISE Transactions on Computing Practices
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    • v.23 no.5
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    • pp.299-303
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    • 2017
  • By piling up hidden layers in artificial neural networks, deep learning is delivering outstanding performances for high-level abstraction problems such as object/speech recognition and natural language processing. Alternatively, deep-learning users often struggle with the tremendous amounts of time and resources that are required to train deep neural networks. To alleviate this computational challenge, many approaches have been proposed in a diversity of areas. In this work, two of the existing Apache Spark-based acceleration frameworks for deep learning (SparkNet and DeepSpark) are compared and analyzed in terms of the training accuracy and the time demands. In the authors' experiments with the CIFAR-10 and CIFAR-100 benchmark datasets, SparkNet showed a more stable convergence behavior than DeepSpark; but in terms of the training accuracy, DeepSpark delivered a higher classification accuracy of approximately 15%. For some of the cases, DeepSpark also outperformed the sequential implementation running on a single machine in terms of both the accuracy and the running time.

Implementation of Data Protocol Conversion System for High-end CMOS Image Sensors Equipped with SMIA CCP2 Serial Interface (SMIA CCP2 직렬 인터페이스를 가지는 고기능 이미지 센서를 위한 데이터 프로토콜 변환 시스템의 구현)

  • Kim, Nam-Ho;Park, Hyun-Sang
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.10 no.4
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    • pp.753-758
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    • 2009
  • Recently the high-end CMOS image sensors are developed, conforming to the SMIA CCP2 specification, which is a high-speed low-power serial interface based on LVDS technology. But this kind of technology trend makes the existing equipments are no longer useful, although their capability is still good enough to handle the recent image sensors if there was no interfacing problem. In this paper, we propose and realize a data protocol conversion system that translates the SMIA CCP2 serial signals into the existing 10-bit parallel signals. The proposed system is composed of a de-serializer and a FPCA chip, and thus can be constructed on a small PCB which enables easy integration between the existing equipments and the new high-end image sensors. Besides, the maximum transfer rate by the SMIA specification is also achieved on the implemented system. So it is expected that the implemented system can be used as a general-purpose protocol converter in a variety of sensor-related application fields.

Implementation of Leakage Monitoring System Using ZigBee (ZigBee를 적용한 누전상태 모니터링시스템 구현)

  • Ju, Jae-han;Na, Seung-kwon
    • Journal of Advanced Navigation Technology
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    • v.21 no.1
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    • pp.107-112
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    • 2017
  • In recent years, electric shock accidents due to electric leakage currents of household appliances such as computers, TVs, refrigerators, and LED lights are continuously occurring in homes and industrial buildings. And it is not easy to check the leakage current of each household appliances connected in parallel at the rear end of the module. In addition, the leakage current flowing through the path of the normal current other than the existing current leakage circuit breakers are installed in the distribution box, only the function to cut off the power when the leakage. Therefore, there are various disasters such as electric shock and fire caused by short circuit of household appliances, and the risk of such leakage current is seriously presented. In this paper, we propose a method to implement a leakage monitoring system that can be monitored at all times using Zigbee communication based on IEEE 80215.4, which has advantages in low power and low cost among short range wireless communication systems.

Design and Implementation of KDSM(KAIST Distributed Shared Memory) System (KDSM(KAIST Distributed Shared Memory) 시스템의 설계 및 구현)

  • Lee, Sang-Kwon;Yun, Hee-Chul;Lee, Joon-Won;Maeng, Seung-Ryoul
    • Journal of KIISE:Computer Systems and Theory
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    • v.29 no.5
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    • pp.257-264
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    • 2002
  • In this paper, we give a detailed description of KDSM(KAIST Distributed Shared Memory) system. KDSM is implemented as a user-level library running on Linux 2.2.13, and TCP/IP is used for communication. KDSM uses page-based invalidation protocol, multiple-writer protocol, and supports HLRC(Home-based Lazy Release Consistency) memory consistency model. To evaluate performance of KDSM, we executed 4 scientific applications and compared the result to JLAJLA. The results showed that performance of KDSM almost equal to JIAJIA for 2 applications and performance of KDSM is better than JIAJIA for 2 applications.

Hybrid FFT processor design using Parallel PD adder circuit (병렬 PD가산회로를 이용한 Hybrid FFT 연산기 설계)

  • 김성대;최전균;안점영;송홍복
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2000.10a
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    • pp.499-503
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    • 2000
  • The use of Multiple-Valued FFT(Fast fourier Transform) is extended from binary to multiple-valued logic(MVL) circuits. A multiple-valued FFT circuit can be implemented using current-mode CMOS techniques, reducing the transitor, wires count between devices to half compared to that of a binary implementation. For adder processing in FFT, We give the number representation using such redundant digit sets are called redundant positive-digit number representation and a Redundant set uses the carry-propagation-free addition method. As the designed Multiple-valued FFT internally using PD(positive digit) adder with the digit set 0,1,2,3 has attractive features on speed, regularity of the structure and reduced complexities of active elements and interconnections. for the mutiplier processing, we give Multiple-valued LUT(Look up table)to facilitate simple mathmatical operations on the stored digits. Finally, Multiple-valued 8point FFT operation is used as an example in this paper to illuatrates how a multiple-valued FFT can be beneficial.

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EU Water Framework Directive-River Basin Management Planning in Ireland

  • Earle, R.;Almeida, G.
    • Environmental Engineering Research
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    • v.15 no.2
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    • pp.105-109
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    • 2010
  • The European Union (EU) Water Framework Directive (WFD) (2000/60/EC) was transposed into Irish law by Statutory Instrument Nos. 722 of 2003, 413 of 2005 and 218 of 2009, which set out a new strategy and process to protect and enhance Ireland's water resources and water-dependent ecosystems. The Directive requires a novel, holistic, integrated, and iterative process to address Ireland's natural waters based on a series of six-year planning cycles. Key success factors in implementing the Directive include an in-depth and balanced treatment of the ecological, economic, institutional and cultural aspects of river basin management planning. Introducing this visionary discipline for the management of sustainable water resources requires a solemn commitment to a new mindset and an overarching monitoring and management regime which hitherto has never been attempted in Ireland. The WFD must be implemented in conjunction with a myriad of complimentary directives and associated legislation, addressing such key related topics as flood/drought management, biodiversity protection, land use planning, and water/wastewater and diffuse pollution engineering and regulation. The critical steps identified for river basin management planning under the WFD include: 1) characterization and classification of water bodies (i.e., how healthy are Irish waters?), 2) definition of significant water pressures (e.g., agriculture, forestry, septic tanks), 3) enhancement of measures for designated protected areas, 4) establishment of objectives for all surface and ground waters, and 5) integrating these critical steps into a comprehensive and coherent river basin management plan and associated programme of measures. A parallel WFD implementation programme critically depends on an effective environmental management system (EMS) approach with a plan-do-check-act cycle applied to each of the evolving six-year plans. The proactive involvement of stakeholders and the general public is a key element of this EMS approach.

Implementation of a GPU Cluster System using Inexpensive Graphics Devices (저가의 그래픽스 장치를 이용한 GPU 클러스터 시스템 구현)

  • Lee, Jong-Min;Lee, Jung-Hwa;Kim, Seong-Woo
    • Journal of Korea Multimedia Society
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    • v.14 no.11
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    • pp.1458-1466
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    • 2011
  • Recently the research on GPGPU has been carried out actively as the performance of GPUs has been increased rapidly. In this paper, we propose the system architecture by benchmarking the existing supercomputer architecture for a cost-effective system using GPUs in low-cost graphics devices and implement a GPU cluster system with eight GPUs. We also make the software development environment that is suitable for the GPU cluster system and use it for the performance evaluation by implementing the n-body problem. According to its result, we found that it is efficient to use multiple GPUs when the problem size is large due to its communication cost. In addition, we could calculate up to eight million celestial bodies by applying the method of calculating block by block to mitigate the problem size constraint due to the limited resource in GPUs.