• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
• /
• v.20 no.6
• /
• pp.104-110
• /
• 2006

In this paper, we proposed the micro web-server implementation on Strong ARM processor with embedded Linux. The parallel port connecting parallel I/O is controlled via HTTP protocol and web browser program HTTP protocol with Linux, the micro web server program and port control program are installed on-board memory using CGI to be accessed by web browser. The processor parallel input port is monitored and parallel output port is controlled from remote hosts via HTTP protocol. The result of the proposed embedded micro-web server can be used in remote automation systems, distributed control via internet using web browser.

• Korean Journal of Computational Design and Engineering
• /
• v.13 no.3
• /
• pp.217-226
• /
• 2008

Web Services for CAD (WSC) aims at interoperation with CAD systems based on Web Services. This paper introduces one part of WSC which enables remote users to retrieve assembly model data using Web Services. However, retrieving assembly model data takes long time. To resolve this problem, this paper proposes using parallel Web Services. As assembly models comprise a set of part models, it is easy to separate the problem domain into smaller problems. In addition, Web Services inherently supports distributed computing. This characteristic makes the parallel processing of Web Services easy. Firstly, the implementation of WSC which retrieves assembly model data based parallel Web Services is shown. And then, for the comparison, the experiments on the retrieval of assembly model data based on single Web Services and parallel Web Services are shown.

• The Transactions of the Korean Institute of Electrical Engineers P
• /
• v.58 no.4
• /
• pp.623-626
• /
• 2009

In this paper, we applied new analog viterbi decoder to decode PR(1,2,2,1) signal for DVD and analyze the specific and signal characteristics. We implemented the parallel analog viterbi decoder and the convolution digital viterbi decoder(the digital PRML) utilizing the technology of analog parallel processing circuits. The proposed analog viterbi decoder can replace the conventional digital viterbi decoder by a new one. Our circuits design the low distortion and the high accuracy over the previous implementation. Through the parallel structure of the proposed viterbi decoder, we got the achievement of the decoding speed by the multiple times.

• Structural Engineering and Mechanics
• /
• v.5 no.5
• /
• pp.635-644
• /
• 1997

The paper reviews the implementation and evaluation of exact methods for the computation of transcendental structural eigenvalues, i.e., critical buckling loads and natural frequencies of undamped vibration, on multiple instruction, multiple data parallel computers with distributed memory. Coarse, medium and fine grain parallel methods are described with illustrative examples. The methods are compared and combined into hybrid methods whose performance can be predicted from that of the component methods individually. An indication is given of how performance indicators can be presented in a generic form rather than being specific to one particular parallel computer. Current extensions to permit parallel optimum design of structures are outlined.

• Proceedings of the KIPE Conference
• /
• 1998.07a
• /
• pp.90-94
• /
• 1998

The parallel inverter is popularly used because of its fault-tolerance capability, high-current outputs at constant voltages and system modularity. The conventional parallel inverter usually employes active and reactive power control or frequency and voltage droop control. However, these approaches have the disadvantages that the response time of parallel inverter control is slow against load and system parameter variation to calculate active, reactive power, frequency and voltage. This paper describes a novel control scheme for power equalization in parallel connected inverter. The proposed scheme has a fast power balance control response, a simplicity of implementation, and inherent peak current limiting capability since it employes a instantaneous current/voltage control with output voltage and current balance and output voltage regulation. A design procedure for the proposed parallel inverter controller is presented. Futhermore, the proposed control scheme is verified through the simulation in various cases such as the system parameter variation, the control parameter variation and the nonlinear load condition.

• Proceedings of the KIPE Conference
• /
• 1998.10a
• /
• pp.176-181
• /
• 1998

The parallel inverter is popularly used because of its fault-tolerance capability, high-current outputs at constant voltages and system modularity. The conventional parallel inverter usually employs active and reactive power control of frequency and voltage droop control. However, these approaches have the disadvantages that the response time of parallel inverter control is slow against load and system parameter variation to calculate active, reactive power, frequency and voltage. This paper describes a novel control scheme for power equalization in parallel-connected inverter. The proposed scheme has a fast power balance control response, a simplicity of implementation, and inherent peak current limiting capability since it employees an instantaneous current/voltage control with output voltage and current balance and output voltage regulation. A design procedure for the proposed parallel inverter controller is presented. Furthermore, the proposed control scheme is verified through the experiment in various cases such as the system parameter variation, the control parameter variation and the nonlinear load condition.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.21 no.8
• /
• pp.2077-2089
• /
• 1996

In this paper, a memory organization and its control method are proposed for the implementation of parallel Virterbi decoders. The design is mainly focused on lowering the hardware complexity of a parallel Viterbi decoder which is to reduce the decoding speed. The memories requeired in a Viterbi decoder are the SMM(State Metric Memory) and the TBM(Traceback Memory);the SMM for storing the path metrics of states and the TBM for storing the survial path information. A general parallel Viterbi decoder for high datarate usually consists of multiple ACS (Add-Compare-Select) units and their corresponding memeory modules.for parallel ACS units, SMMs and TBMs are partitioned into smaller independent pairs of memory modules which are separately interleaved to provide the maximum processing speed. In this design SMMs are controlled with addrss generators which can simultaneously compute addresses of the new path metrics. A bit shuffle technique is employed to provide a parallel access to the TBMs to store the survivor path informations from multiple ACS modules.

• Journal of Institute of Control, Robotics and Systems
• /
• v.15 no.9
• /
• pp.952-958
• /
• 2009

This article presents a combined structure of serial and parallel mechanisms for a humanoid robot. The 3 DOF parallel structure is designed and added to the waist of the humanoid robot arm to give flexible bending and rotating motions. Forward and inverse kinematics of a serial and parallel robot have been analyzed to generate motions. Simulation studies of verifying kinematics solutions of the parallel robot have been done. Experimental studies of mimicking shake-hands motion have been conducted to show the feasibility and usability of the combined structure.

• Journal of Institute of Control, Robotics and Systems
• /
• v.15 no.5
• /
• pp.488-495
• /
• 2009

This paper presents a fast feature extraction method for autonomous mobile robots utilizing parallel processing and based on OpenMP, SSE (Streaming SIMD Extension) and CUDA programming. In the first step on CPU version, the algorithms and codes are optimized and then implemented by parallel processing. The parallel algorithms are debugged to maintain the same level of performance and the process for extracting key points and obtaining dominant orientation with respect to key points is parallelized. After extraction, a parallel descriptor via SSE instructions is constructed. And the GPU version also implemented by parallel processing using CUDA based on the SIFT. The GPU-Parallel descriptor achieves an acceleration up to five times compared with the CPU-Parallel descriptor, but it shows the lower performance than CPU version. CPU version also speed-up the four and half times compared with the original SIFT while maintaining robust performance.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.16 no.9
• /
• pp.893-900
• /
• 1991

And this system is compared with past knapsack system by implementation of low density attack in Brickell and Lagarias, Odlyzko’s method. Also the VLSI architecture for parallel implementation of this linearly shift knapsack system is presented