• 제어로봇시스템학회:학술대회논문집
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• 1997.10a
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• pp.1624-1627
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• 1997

The 6-DOF parallel manipulator is a closed-kindmatic chain robot manipulator that is capable of providing high structural rigidity and positional accuracy. Because of its advantage, the parallel manipulator have been widely used in many engineering applications such as vehicle/flight driving simulators, rogot maniplators, attachment tool of machining centers, etc. However, the kinematic analysis for the implementation of a real-time controller has some problem because of the lack of an efficient lagorithm for solving its highly nonliner forward kinematic equation, which provides the translational and orientational attitudes of the moveable upper platform from the lenght of manipulator linkages. Generally, Newton-Raphson method has been widely sued to solve the forward kinematic problem but the effectiveness of this methodology depend on how to set initial values. This paper proposes a hybrid method using genetic algorithm(GA) and Newton-Raphson method to solve forward kinematics. That is, the initial values of forward kinematics solution are determined by adopting genetic algorithm which can search grobally optimal solutions. Since determining this values, the determined values are used in Newton-Raphson method for real time calcuation.

• Proceedings of the IEEK Conference
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• 2000.06c
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• pp.97-100
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• 2000

As network resources have become faster and demands for multimedia service through network have increased, the demand for Media server system has increased. These kinds of media server solve their bottle neck problem of internal storage device by using parallel system which takes advantage of fast network resource. Many vendors have suggested each of their media server system to solve these problem radically, but most of them require major modification of infra component and additional drawback has added. For example, storage mechanism for specific media requires new file system which is totally different from traditional one, and algorithm for enhancing performance may not suit for traditional operating system environment. In this paper, we designed a parallel media server based on web interface of traditional system and implemented a program for media server. Implemented server system performs parallel processing through web interface without any modification of traditional system, and controls which is related to merging load by distributed data is charged only to client and control server and consequently load of storage server can be minimized. And also, data transfer protocol for streaming media includes Retransfer algorithm and client Admission control policy relevant to performance of whole system.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 1999.11b
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• pp.173-178
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• 1999

The Trellis Coded Modulation(TCM) allows the considerable achievements of coding gains compare with conventional multi-level modulation without compromising bandwidth efficiency. In this paper, we are presented a design of the parallel Viterbi decoder for 16-QAM TCM decoder with large constraint length (K=9), which can be applicable for the Digital Audio Broadcasting(DAB) receiver. As a mid-term result, a parallel Branch Metric Calculator (BMC)can compute 16 BMs within 3 clocks and a parallel 16 Add-Compare-Selects (ACS) unit can compute in a single clock. And also, two 256 Path Metric Memories (PMM) 32 Trace Back(TB) memories are specially designed with shuffle exchange switches for 16 parallel accesses. As a VHDL simulation, we can find the correctness of proposed model, which can be operated 16 S per symbol. Now, we are performing the hardware reduction for realtime operation and FPGA implementation.

• Journal of Korea Multimedia Society
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• v.6 no.7
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• pp.1189-1199
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• 2003

This paper presents a new method for the motion detection of vehicles using hierarchical motion estimation and parallel processing. It captures the road image by using a CMOS sensor. It divides the captured image into small blocks and detects the motion of each block by using a block-matching method which is based on a hierarchical motion estimation and parallel processing for the real-time processing. The parallelism is achieved by using tile pipeline and the data flow technique. The proposed method has been implemented by using an embedded system. The proposed block matching algorithm has been implemented on PLDs(Programmable Logic Device) and clustering algorithm has been implemented by ARM processor. Experimental results show that the proposed system detects the motion of vehicles in real-time.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2004.10a
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• pp.299-303
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• 2004

In our pervious paper, a new parallel-type spherical 3-degree-of-freedom mechanism consisting of a two-degree-of-freedom parallel module and a serial RRR subchain was proposed[1]. In this paper, its improved version is suggested and implemented. Differently from the previous 3-dof spherical mechanism, gear chains are incorporated into the current version of the mechanism to drive the distal revolute joint of the serial subchain from the base of the mechanism and in fact, the modification significantly improves kinematic characteristics of the mechanism within its workspace. Firstly, after a brief description on its structure, the closed-form solutions of both the forward and the reverse position analysis are derived. Secondly, the first-order kinematic model of the mechanism for the inputs which are assumed to be located at the base is derived. Thirdly, through the simulations of the kinematic analysis via. kinematic isotropic index, it is confirmed that the mechanism has much more improved isotropic properties throughout the workspace of the mechanism than the previous mechanism in [1]. Lastly, the proposed mechanism is implemented to verify the results from this analysis.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.10 no.4
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• pp.288-294
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• 2017

Recently, deep learning using convolutional neural network (CNN) has been extensively studied in image recognition. Convolution consists of addition and multiplication. Multiplication is computationally expensive in hardware implementation, relative to addition. It is also important factor limiting a chip design in an embedded deep learning system. In this paper, I propose a parallel-addition processing algorithm that converts grayscale images to the superposition of binary images and performs convolution only with addition. It is confirmed that the convolution can be performed by a parallel-addition method capable of reducing the processing time in experiment for verifying the availability of proposed algorithm.

• Korean Journal of Computational Design and Engineering
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• v.16 no.3
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• pp.236-245
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• 2011

Many researchers have recently studied multi-level formulation strategies to solve the MDO problems and they basically distributed the coupling compatibilities across all disciplines, while single-level formulations concentrate all the controls at the system-level. In addition, approximation techniques became remedies for computationally expensive analyses and simulations. This paper studies comparisons of the MDO methods with respect to computing performance considering both conventional sequential and modem distributed/parallel processing environments. The comparisons show Individual Disciplinary Feasible (IDF) formulation is the most efficient for sequential processing and IDF with approximation (IDFa) is the most efficient for parallel processing. Results incorporating to popular design examples show this finding. The author suggests design engineers should firstly choose IDF formulation to solve MDO problems because of its simplicity of implementation and not-bad performance. A single drawback of IDF is requiring more memory for local design variables and coupling variables. Adding cheap memories can save engineers valuable time and effort for complicated multi-level formulations and let them free out of no solution headache of Multi-Disciplinary Analysis (MDA) of the Multi-Disciplinary Feasible (MDF) formulation.

• Journal of Internet Computing and Services
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• v.14 no.6
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• pp.41-47
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• 2013

GP-GPUs are general purposed GPUs for numerical computation based on multiple threads which are originally for graphic processing. GP-GPUs provide cache memory in a form of shared memory which user programs can access directly, unlikely typical cache memory. In this research, we implemented the parallel block LU decomposition program to utilize cache memory in GP-GPUs. The parallel blocked LU decomposition program designed with Nvidia CUDA C run 7~8 times faster than nun-blocked LU decomposition program in the same GP-GPU computation environment.

• Journal of the Korean Society for Precision Engineering
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• v.22 no.11 s.176
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• pp.72-81
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• 2005

A new spherical-type 3-degree-of-freedom parallel mechanism consisting of a two degree-of-freedom parallel module and a serial module is proposed. Two alternative designs for the serial sub-chain are suggested and compared. The first design employs RU joint arrangement for the serial sub chain structure. The second design incorporates a gear chain to drive the distal revolute joint of the serial sub-chain from the base platform of the mechanism. This modification significantly improves kinematic characteristics of the mechanism within its workspace. Firstly, the closed-form solutions of both the forward and the reverse position analysis are derived. Secondly, the first-order kinematic model with respect to three inputs which are located at the base is derived. Thirdly, it is confirmed through simulation that the modified mechanism has much more improved isotropic characteristic throughout the workspace of the mechanism. Lastly, the proposed mechanism is implemented to verify the results from this analysis.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.17 no.12
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• pp.1484-1493
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• 1992

In this paper, we propose the polarization coding of optical logic gates using filters and LCTV's, and represent the real-time system of an optical parallel adder to improve a carry propagation delay time. We fabricated a polarization filter for the polarization coding of a cell and an electrical system instead of an optical flip-flop which was necessary to an optical parallel adder. We used an optical fiber to play a part of decoding mask and interconnections in an optical parallel adder. The experimental results show that the polarization coding of a cell can represent 16 optical logic functions and that the implemented optical parallel adder can operate in real-time.