• The Journal of Korean Institute of Communications and Information Sciences
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• v.14 no.4
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• pp.388-397
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• 1989

This paper describes an intelligent iterative parallel algorithm for solving large sparse linear systems of equations, and proposes a ststic dataflow computer architechture for the implementation of the algorithm. Implemented with the Jacobi interative method, the intelligent algorithm reduces the parallel execution time by reducing the individual inner product operation time.

• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.282-284
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• 1988

In this paper, a method for constructing parallel-in, parallel-out multipliers in GF($2^{m}$) is presented. The proposed system is composed of two operational parts by using shift register. One is a multiplicative arithmetical operation part capable of the multiplicative arithmetic and modulo 2 operation to all product terms with the same degree. And the other is an irreducible polynomial operation part to outputs from the multiplicative arithmetical operation part. Since the total hardware is linearly m dependant to an GF($2^{m}$), this system has a reasonable merit when m increases. And also this system is suited for VLSI implementation due to simple, regular, and concurrent properties.

• Journal of the Korea Society of Computer and Information
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• v.11 no.2 s.40
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• pp.341-349
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• 2006

These day, Internet Recruiting needs negotiation of recruiting items. So in this paper, Internet Recruiting Negotiation System(IRNS) proposes multilateral negotiation that substitutes applicants and employers. Previous NSS uses preference value of multi-attribute and sequential negotiation. But proposed IRNS uses parallel negotiation of multi-attribute. parallel negotiation supplies multi-attribute negotiation including single-attribute and results of parallel negotiation. This paper proposes effective negotiation using weight strategy of multi-attribute.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.6
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• pp.10-16
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• 1994

In case of off-line character recognition with statistical method, the character recognition speed for Korean or Chinese characters is slow since the amount of calculation is huge. To improve this problem, we seperate the recognition steps into several functional stages and implement them with hardwares for each stage so that all the stages can be processed with pipline structure. In accordance with temporal parallel processing, a high speed character recognition system can be implemented. In this paper, we implement a classification hardware, which is one of the several functional stages, to improve the speed by parallel structure with multiple DSPs(Digital Signal Processors). Also, it is designed to be able to expand DSP boards in parallel to make processing faster as much as we wish. We implement the hardware as an add-on board in IBM-PC, and the result of experiment is that it can process about 47-times and 71-times faster with 2 DSPs and 3 DSPs respectively than the IBM-PC(486D$\times$2-66MHz). The effectiveness is proved by developing a high speed OCR(Optical Character Recognizer).

• Journal of Power Electronics
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• v.14 no.5
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• pp.827-833
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• 2014

This study proposes a coupled inductor method for the parallel operation of a power conditioning system (PCS). When primary and secondary currents flow in the same direction in a coupled inductor, total flux and inductance are cancelled; when currents flow in opposite directions, each flux becomes an individual inductor. These characteristics are applied in the parallel operation of a PCS. To connect at a grid code, abnormal current, which is barred under the grid connection code, is blocked by using a coupled inductor. A design based on the capacity and current duration time of a PCS is verified through hardware implementation. Experiment results show the effectiveness of variance reduction.

• The Transactions of the Korea Information Processing Society
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• v.2 no.5
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• pp.701-710
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• 1995

A thinning algorithm is a very important procedure in order to increase recognition rate in the character recognition. This paper is the study of a parallel thinning algorithm available for the recognition of various characters, and it proposes the parallel thinning algorithm using the 8-neighbors connectivity value. Characteristics of the proposed algorithm are easiness of implementation of parallelism, the result of thinning is perfectly-8 connectivity and represented by numeric information. The proposed algorithm is very suitable for characters having many curve segments such as English, Japanese etc. Performance evaluation was performed by the measure of similarity to reference skeleton.

• Proceedings of the KIEE Conference
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• 1998.11b
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• pp.575-578
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• 1998

In this paper, we propose a VLSI architecture of Reed-Solomon decoder. Our goal is the development of an architecture featuring parallel and pipelined processing to improve the speed and low power design. To achieve the this goal, we analyze the RS decoding algorithm to be used parallel and pipelined processing efficiently, and modified the Euclid's algorithm arithmetic part to apply the parallel structure in RS decoder. The overall RS decoder are compared to Shao's, and we show the 10% area efficiency than Shao's time domain decoder and three times faster, in addition, we approve the proposed RS decoders with Altera FPGA Flex 10K-50, and Implemeted with LG 0.6{\mu}$ processing.

• Proceedings of the Computational Structural Engineering Institute Conference
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• 2000.10a
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• pp.40-47
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• 2000

One of the drawbacks of GA-based structural optimization is that the fitness evaluation of a population of hundreds of individuals requiring hundreds of structural analyses at each CA generation is computational too expensive. Therefore, a parallel genetic algorithm is developed for structural optimization on a cluster of personal computers in this paper. Based on the parallel genetic algorithm, a population at every generation is partitioned into a number of sub-populations equal to the number of slave computers. Parallelism is exploited at sub-population level by allocationg each sub-population to a slave computer. Thus, fitness of a population at each generation can be concurrently evaluated on a cluster of personal computers. For implementation of the algorithm a virtual distributed computing system in a collection of personal computers connected via a 100 Mb/s Ethernet LAN. The algorithm is applied to the minimum weight design of a steel structure. The results show that the computational time requied for serial GA-based structural optimization process is drastically reduced.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.66 no.3
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• pp.599-604
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• 2017

Nowadays reactance method is being used as a technique for fault location in parallel feeding AC traction power system. However, implementation of this method requires a large number of field tests(ground fault) which is a huge burden on the operators. This paper presents a new estimation technique using quadratic interpolation to reduce number of times for field test and improves the accuracy of fault location. To verify a new technique, we solve AT feeding circuit and model it using PSCAD/EMTDC. Finally this paper conducts a comparative analysis of usefulness between a new technique and real field data.

• Journal of Sensor Science and Technology
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• v.24 no.2
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• pp.107-112
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• 2015

HIGHT is an 64-bit block cipher, which is suitable for low power and ultra-light implementation that are used in the network that needs the consideration of security aspects. This paper presents a parallel key scheduler that generates the whitening keys and subkeys simultaneously for both encryption and decryption processes. We construct the reverse LFSR and key generation blocks to generate the keys for decryption process. Then, the new key scheduler is made by sharing the common logics for encryption and decryption processes to minimize the increase in hardware complexity. From the simulation results, the logic size is increased 1.31 times compared to the conventional HIGHT. However, the performance of HIGHT including the proposed key scheduler can be increased by two times compared to the conventional counterpart.