• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.9
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• pp.45-53
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• 2015

Adaptive support-weight based algorithm can produce better disparity map compared to generic area-based algorithms and also can be implemented as a realtime system. In this paper, we propose a realtime system based on geodesic support-weight which performs better segmentation of objects in the window. The data scheduling is analyzed for efficient hardware design and better performance and the parallel architecture for weight update which takes the longest delay is proposed. The exponential function is efficiently designed using a simple step function by careful error analysis. The proposed architecture is designed with verilogHDL and synthesized using Donbu Hitek 0.18um standard cell library. The proposed system shows 2.22% of error rate and can run up to 260Mhz (25fps) operation frequency with 182K gates.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.45 no.5
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• pp.1-7
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• 2008

The general bus architecture consists of masters, slaves, arbiter, decoder and so on in shared bus. Specially, as several masters do not concurrently receive the right of bus usage, the arbiter plays an important role in arbitrating between shared bus and masters. Fixed priority, round-robin, TDMA and Lottery methods are developed in general arbitration policies, which lead the efficiency of bus usage in shared bus. On the other hand, the bus architecture can be modified to maximize the system performance. In the paper, we propose the flying master bus architecture that supports the parallel bus communication and analyze its merits and demerits following various arbitration policies that are mentioned above, compared with normal shared bus. From the results of performance verification using TLM(Transaction Level Model), we find that more than 40% of the data communication performance improves, regardless of arbitration policies. As the flying master bus architecture advances its studies and applies various SoCs, it becomes the leading candidate of the high performance bus architecture.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.9
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• pp.1709-1716
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• 2007

In this paper, ADC with multi SHA structure is proposed for high speed operation. The proposed structure incorporates a multi SHA block that consists of multiple SHAs of identical characteristics in parallel to improve the conversion speed. The designed multi SHA is operated by non-overlapping clocks and the sampling speed can be improved by increasing the number of multiplexed SHAs. Pipelined A/D converter, applying the proposed structure, is designed to satisfy requirement of analog front-end of VDSL modem. The measured INL and DNL of designed A/D converter are $0.52LSB{\sim}-0.50LSB$ and $0.80LSB{\sim}-0.76LSB$, respectively. It satisfies the design specifications for VDSL modems. The simulated SNR is about 66dB which corresponds to a 10.7 bit resolution. The power consumption is 24.32mW.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.19 no.1
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• pp.247-252
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• 2019

The diffraction properties of optical signals by multi-layered periodic structures is formulated in two-dimensional space by using Fourier expansions associated with basic grating profile. The fields in each layer are then expressed in terms of characteristic modes, and the complete solution is found rigorously by using a modal transmission-line theory(MTLT) to address the pertinent boundary-value problems. Such an approach can treat periodic arbitrary gratings containing arbitrarily shaped dielectric components, which may generally have optical properties along directions that are parallel or perpendicular to the multi-layers. This paper illustrates the present approach by comparing our numerical results with data reported in the past for simple periodic circular 2D structures. In addition, this proposed theory can apply easily for more complex configurations, which include multiple periodic regions with several possible canonic shapes and high dielectric constants.

• The Journal of the Korea institute of electronic communication sciences
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• v.14 no.2
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• pp.417-424
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• 2019

This paper presents the design of a JPEG-LS codec for lossless image compression from AR/VR device. The proposed JPEG-LS(: LosSless) codec is mainly composed of a context modeling block, a context update block, a pixel prediction block, a prediction error coding block, a data packetizer block, and a memory block. All operations are organized in a fully pipelined architecture for real time image processing and the LOCO-I compression algorithm using improved 2D approach to compliant with the SBT coding. Compared with a similar study in JPEG-LS, the Block-RAM size of proposed STB-FLC architecture is reduced to 1/3 compact and the parallel design of the predication block could improved the processing speed.

• The Journal of the Korea institute of electronic communication sciences
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• v.18 no.2
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• pp.361-366
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• 2023

Apache Hadoop, a representative framework for distributed processing of big data, has the advantage of increasing cluster size up to thousands of nodes to improve parallel distributed processing performance. However, reducing the size of the cluster is limited to the extent of permanently decommissioning nodes with defects or degraded performance, so there are limitations to operate multiple nodes flexibly in small clusters. In this paper, we discuss the problems that occur when removing nodes from the Hadoop cluster and propose a dynamic down-scaling technique to manage the distributed cluster more flexibly. To do this, we design and implement a modified Hadoop system and interfaces to support dynamic down-scaling of the cluster which supports temporary pause of a node and reconnection of it when necessary, rather than decommissioning the node when removing a node from the Hadoop cluster. We have verified that effective downsizing can be performed without performance degradation based on experimental results.

• KIPS Transactions on Software and Data Engineering
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• v.6 no.1
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• pp.1-8
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• 2017

Given a multi-dimensional dataset of tuples, a skyline query returns a subset of tuples which are not 'dominated' by any other tuples. Skyline query is very useful in Big data analysis since it filters out uninteresting items. Much interest was devoted to the MapReduce-based parallel processing of skyline queries in large-scale distributed environment. There are three requirements to improve parallelism in MapReduced-based algorithms: (1) workload should be well balanced (2) avoid redundant computations (3) Optimize network communication cost. In this paper, we introduce MR-SEAP (MapReduce sample Skyline object Equality Angular Partitioning), an efficient angular space partitioning based skyline query processing using sampling-based pruning, which satisfies requirements above. We conduct an extensive experiment to evaluate MR-SEAP.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.6
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• pp.1095-1100
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• 2008

In a process of insect foot recognition, footprint segments as basic areas for recognition need to be extracted from scanned insect footprints and appropriate features should be found from the footprint segments in order to discriminate kinds of insects, because the characteristics of the features are important to classify insects. In this paper, we propose methods for automatic footprint segmentation and feature extraction. We use a Trace transform method in order to find out appropriate features from the extracted segments by the above methods. The Trace transform method builds a new type of data structure from the segmented images by functions using parallel trace lines and the new type of data structure has characteristics invariant to translation, rotation and reflection of images. This data structure is converted to Triple features by Diametric and Circus functions, and the Triple features are used for discriminating patterns of insect footprints. In this paper, we show that the Triple features found by the proposed methods are enough distinguishable and appropriate for classifying kinds of insects.

• Journal of Korea Water Resources Association
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• v.47 no.7
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• pp.599-614
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• 2014

In this study, two dimensional finite volume model was parallelized to improve computing time, which has been developed to be able to apply for the mixed meshes of triangle and quadrilateral. MPI scheme which is free from limitation of the number of cores was applied, and non-blocking point-to-point communication was used for fluxes and time steps calculation domain. The developed model is applied to analyze dam break in a L-shaped experimental channel with $90^{\circ}$ bend and Malpasset dam breach event to calibrate the consistency between parallelized model and existing model and examine the speed-up and efficiency of computing time. Computational speed-up about the size of the input data was considered by simulating 4 cases classified by the number of meshes, Consequently, the simulation results reached a satisfactory accuracy compared to measured data and the results from existing model, and achieved more than 3 times benefit of computational speed-up against computing time of existing model. Simulation results of 3 cases classified by the size of input data lead us to the conclusion that it is important to use proper size of input data and the number of process in order to minimize the communication overhead.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.4
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• pp.41-49
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• 2010

This paper proposes a new high speed SHA-1 architecture using multiple unfolding and pre-computation techniques. We unfolds iterative hash operations to 2 continuos hash stage and reschedules computation timing. Then, the part of critical path is computed at the previous hash operation round and the rest is performed in the present round. These techniques reduce 3 additions to 2 additions on the critical path. It makes the maximum clock frequency of 118 MHz which provides throughput rate of 5.9 Gbps. The proposed architecture shows 26% higher throughput with a 32% smaller hardware size compared to other counterparts. This paper also introduces a analytical model of multiple SHA-1 architecture at the system level that maps a large input data on SHA-1 block in parallel. The model gives us the required number of SHA-1 blocks for a large multimedia data processing that it helps to make decision hardware configuration. The hs fospeed SHA-1 is useful to generate a condensed message and may strengthen the security of mobile communication and internet service.