• The Transactions of the Korea Information Processing Society
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• v.4 no.9
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• pp.2259-2268
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• 1997

Multistage interconnection networks(MINs) provide a high-bandwidth communication between processors and/or memory modules in a cost-effective way. In this paper, we propose a class of multipath MINs, called the Augmented Modified Delta(AMD) network, and analyze its performance and reliability. The salient features of the AMD network include fault-tolerant capability, modular structure, and high performance, which are essential for real-time parallel/distributed processing environments. The class of the AMD network retains well-known characteristics of the Kappa network, but it's design procedure is more systematic. Like Delta networks, all the AMD networks are topologically equivalent with each other.

• Journal of Information Processing Systems
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• v.9 no.2
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• pp.301-314
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• 2013

In a parallel processing system, Multi-stage Interconnection Networks (MINs) play a vital role in making the network reliable and cost effective. The MIN is an important piece of architecture for a multiprocessor system, and it has a good impact in the field of communication. Optical Multi-stage Interconnection Networks (OMINs) are the advanced version of MINs. The main problem with OMINs is crosstalk. This paper, presents the (1) Destination Based Modified Omega Network (DBMON) and the (2) Destination Based Scheduling Algorithm (DBSA). DBSA does the scheduling for a source and their corresponding destination address for messages transmission and these scheduled addresses are passed through DBMON. Furthermore, the performance of DBMON is compared with the Crosstalk-Free Modified Omega Network (CFMON). CFMON also minimizes the crosstalk in a minimum number of passes. Results show that DBMON is better than CFMON in terms of the average number of passes and execution time. DBSA can transmit all the messages in only two passes from any source to any destination, through DBMON and without crosstalk. This network is the modified form of the original omega network. Crosstalk minimization is the main objective of the proposed algorithm and proposed network.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.5
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• pp.1177-1186
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• 2014

Computer-generated hologram (CGH) is to mathematically model optical phenomenon with digital computer. Because it requires huge amount of computational power, a fast and high performance technique is needed. In this paper, we proposed two parallelizations for CGH calculation. The first is to parallelize CGH algorithm in a GPU (general processing unit) and the second is to parallelize multiple GPUs. The proposed algorithm was implemented in GTX780 Ti GPU. It calculates a $1,024{\times}1,024$ hologram with 10K object points for about 24ms.

• Proceedings of the IEEK Conference
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• 2004.08c
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• pp.658-662
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• 2004

This paper proposes an orthogonal reception structure for OS/SS communication with time-shifted m-sequences, and compares the performances of the proposed and conventional receiver. This structure provides two important characteristics to reference user signal with not only increment of auto-correlation value but also cancel of the cross-correlation value out to zero between the reference user and other user signals. In addition, the structure can be easily implemented with the conventional receiver adding an additional integrator path in parallel and an adder that sums the conventional path output and the new path output signal. Hence, the proposed structure can be applied for channel impulse response measurement, and efficiently used for multi-user interference signal cancellation and channel capacity increment by flexible structural inter-working operation, connection or disconnection, of the new path to conventional receiver structure.

• IEIE Transactions on Smart Processing and Computing
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• v.6 no.2
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• pp.133-139
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• 2017

Vehicles have increasingly evolved and become intelligent with convergence of information and communications technologies (ICT). Vehicle communications (VC) has become one of the major necessities for intelligent vehicles. However, VC suffers from serious security problems that hinder its commercialization. Hence, the IEEE 1609 Wireless Access Vehicular Environment (WAVE) protocol defines a security service for VC. This service includes Advanced Encryption Standard-Counter with CBC-MAC (AES-CCM) for data encryption in VC. A high-speed AES-CCM crypto module is necessary, because VC requires a fast communication rate between vehicles. In this study, we propose and implement an efficient AES-CCM hardware architecture for high-speed VC. First, we propose a 32-bit substitution table (S_Box) to reduce the AES module latency. Second, we employ key box register files to save key expansion results. Third, we save the input and processed data to internal register files for secure encryption and to secure data from external attacks. Finally, we design a parallel architecture for both cipher block chaining message authentication code (CBC-MAC) and the counter module in AES-CCM to improve performance. For implementation of the field programmable gate array (FPGA) hardware, we use a Xilinx Virtex-5 FPGA chip. The entire operation of the AES-CCM module is validated by timing simulations in Xilinx ISE at a speed of 166.2 MHz.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.28 no.4
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• pp.415-424
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• 2004

Cooling the electronic equipment is one of the major focal points of the design process and the key to successful product launch. The two-phase loop thermosyphone which is a good candidate among many available options was investigated fur cooling of the high power amplifiers. The system is composed of evaporator which contains 6 parallel cold plates, fan cooled condenser, gas-liquid separator, and interconnecting tubes. Experiments were performed for several refrigerant charging values, hs and as a experiment result, the optimum charging value fur this system was proposed. In order to optimize the system design, the operating cycle pressure and inlet/outlet temperatures of evaporator and condenser are measured and analyzed. The effect of the three parameters such as flow rate and temperature of condenser cooling air, and thermal load on the evaporator are investigated. The lower the operating pressure and the cycle temperatures are also better to prevent the leakage of the system. The system invesigated in this paper can be directly used for cooling of a real unmanned wireless communication station.

• Journal of Sensor Science and Technology
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• v.8 no.1
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• pp.80-88
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• 1999

This paper deals with the position determination problem of stereo camera systems used as a sensor for 3D robotic manipulation. Stereo cameras having parallel rays of sight and been set up on the same baseline are assumed. The distance between the sensor and the space measured is determined so as to get insensitive parameters to the uncertainty of control points used for calibration and to satisfy the error condition set by considering the repeatability of the robot. The baseline width is determined by minimizing the mutual effect of 3D positional error and stereo image coordinate error. Unlike existing techniques, the technique proposed here is developed without complicated constraints and modelling process of the object to be observed. Thus, the technique of this paper is more general and its effectiveness is proved by simulation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.4 no.3
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• pp.627-633
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• 2000

In this paper, the polyphase filter which has micro ripple characteristic in the passband is proposed. This filter consists of the digital all-pass filter of parallel structure and it is the half-band filter with all zeros in unit circle. To approach easily in designing hardware, we determined the coefficients to the 16bit 1.15 format. To evaluate the performance of this filter, we analyzed the phase characteristic in each branch and each filter with small coefficients. Also, we simulated the phase characteristic of passband and stopband, group delay. As the result, we obtained the micro ripple characteristic and linear phase in the passband.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.4 no.3
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• pp.565-573
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• 2000

In this paper, a interdigital microstrip bandpass filter is designed. A interdigital microstrip bandpass filter has many advantages such as insertion return loss, lower return loss, higher frequency selectivity and smaller in size in comparison with the conventional coupled line filter. A interdigital microstrip bandpass filter consists of quasi TEM-mode strip line resonators between parallel ground plant. Each resonator element is a quarter wavelength long of the center frequency and is short circuited at one end and open circuited at the other end. In the filter design, Ensemble software is used. Experimental results show that the bandwidth of interdigital microstrip bandpass filter is 2.52GHz, insertion loss is -1.8dB and return loss is -17.0dB at 11.20Hz.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.67 no.2
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• pp.270-276
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• 2018

Apache Spark is one of the high performance in-memory computing frameworks for big-data processing. Recently, to improve the performance, general-purpose computing on graphics processing unit(GPGPU) is adapted to Apache Spark framework. Previous Spark-GPGPU frameworks focus on overcoming the difficulty of an implementation resulting from the difference between the computation environment of GPGPU and Spark framework. In this paper, we propose a Spark framework based on a heterogenous pipeline computing with OpenCL to further improve the performance. The proposed framework overlaps the Java-to-Native memory copies of CPU with CPU-GPU communications(DMA) and GPU kernel computations to hide the CPU idle time. Also, CPU-GPU communication buffers are implemented with switching dual buffers, which reduce the mapped memory region resulting in decreasing memory mapping overhead. Experimental results showed that the proposed Spark framework based on a heterogenous pipeline computing with OpenCL had up to 2.13 times faster than the previous Spark framework using OpenCL.