• Journal of Institute of Control, Robotics and Systems
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• v.19 no.11
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• pp.979-983
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• 2013

The three-dimensional measurement method of confocal systems is a spot scanning method which has a high resolution and good illumination efficiency. However, conventional confocal systems had a weak point in that it has to perform XY axis scanning to achieve FOV (Field of View) vision through spot scanning. There are some methods to improve this problem involving the use of a galvano mirror [1], pin-hole array, etc. Therefore, in this paper we propose a method to improve a parallel mode confocal system using a micro-lens and pin-hole array in a dual microscope configuration. We made an area scan possible by using a combination MLA (Micro Lens Array) and pin-hole array, and used an objective lens to improve the light transmittance and signal-to-noise ratio. Additionally, we made it possible to change the objective lens so that it is possible to select a lens considering the reflection characteristic of the measuring object and proper magnification. We did an experiment using 5X, 2.3X objective lens, and did a calibration of height using a VLSI calibration target.

• The Transactions of the Korea Information Processing Society
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• v.7 no.1
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• pp.65-73
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• 2000

This paper deals with a design and performance analysis of a parallel signal processing system based on TMS320C67x. With an emphasis on the board-level design of the processor unit four models are proposed with different memory configurations and internal bus schemes. Several approaches to parallel processing of 2D FFT are also presented to be used for performance analysis. The performance of four board models are estimated and compared in terms of the time spent for local memory access, inter-processor communication, and inter-board communication. The results of performance analysis show that, when performance and implementation complexity are taken into account, the model with both local and shared memories is the most desirable.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.37 no.7
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• pp.1-8
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• 2000

In this paper, we introduce a modified interference cancellation scheme for multiuser detection in CDMA(Code Division Multiple Access). This detector uses SIC(Successive Interference Canceller) scheme and divides the received signals to reduce the delay time. In this proposed structure, the active users are divided into a number of groups. Within each group, parallel detection is performed to estimate the output signal of that group. The estimated output signal due to that group is then subtracted from the received signal and the resulting residual signal is used for the parallel detection of the next group. This parallel and serial cancellation process is repeated until the last group in the stage is completed. The estimated output signals due to all groups except -th group are MAI for the user signals in -th group. Therefore, the estimated output signals due to all groups except th group are subtracted from the received signal, and then the obtained signal becomes the input signal of -th SIC. The proposed RDSIC (Reduced Delay time of Successive Interference Canceller) has performance and complexity close to the SIC, but with much less detection delay.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.1
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• pp.8-16
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• 2020

In this paper, a single-bit 2nd-order delta-sigma modulator with the architecture of cascaded-of-integrator feedforward (CIFF) is proposed for column-parallel analog-to-digital converter (ADC) array used in a low noise CMOS image sensor. The proposed modulator implements two switched capacitor integrators and a single-bit comparator within only 10-㎛ column-pitch for column-parallel ADC array. Also, peripheral circuits for driving all column modulators include a non-overlapping clock generator and a bias circuit. The proposed delta-sigma modulator has been implemented in a 110-nm CMOS process. It achieves 88.1-dB signal-to-noise-and-distortion ratio (SNDR), 88.6-dB spurious-free dynamic range (SFDR), and 14.3-bit effective-number-of-bits (ENOB) with an oversampling ratio (OSR) of 418 for 12-kHz bandwidth. The area and power consumption of the delta-sigma modulator are 970×10 ㎛2 and 248 ㎼, respectively.

• Journal of Korea Society of Industrial Information Systems
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• v.5 no.3
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• pp.117-124
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• 2000

A systolic array is a parallel processing system which consists of processing elements of basic computation capabilities, connected with regular and local communication lines. It has been known that a systolic array is on of effective systems to solve complicated communication problems occurred between densely connected neurons on ANN(Artificial Neural Network). In this paper, a systolic array simulator for the back-propagation ANN, which automatically constructs the proper systolic array for a given number of neurons of the ANN, is designed and constructed. With animation techniques of the simulators, it is easy for users to be able to examine the execution of the back-propagation algorithm on the designed systolic array step by step. Moreover the simulator can perform forward and backward operations of the back-propagation algorithm either in sequence or in parallel on the designed systolic array. Parallel execution can be performed by feeding continuous input patterns and by executing bidirectional propagations on all of processing elements of a systolic array at the same time.

• The Journal of the Korea institute of electronic communication sciences
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• v.14 no.2
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• pp.345-350
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• 2019

This study deals with the design of a modular converter that can convert the output voltage according to the size of the load. The efficiency of the converter depends on the size of the load and is generally less efficient for lower loads. Therefore, it is more efficient to construct a small capacity modular converter than to manufacture a large capacity converter and it determines the capacity of the system through the parallel connection of the converter module according to the load size. In this paper, we will introduce a modular DC / DC converter designed to control the number of modules according to the load. A programmable resistor is placed at the output of the module for parallel connection of the module, and the voltage is regulated by adjusting the variable resistor. A system controlled in this way was found to exhibit an efficiency improvement of about 32%.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.22 no.1
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• pp.95-101
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• 2022

The two-sided assembly line balancing problem is a kind of NP-hard problem. This problem primarily can be solved metaheuristic method. This paper suggests parallel clustering algorithm that each left and right-sided workstation assigned by operations with T_i = c^* ± α < c, c^* = ${\lceil}$W/m^*${\rceil}$ such that M^* = ${\lceil}$W/c${\rceil}$ for precedence diagram of two-sided assembly line with total complete time W and cycle time c. This clustering performs forward direction from left to right or reverse direction from right to left. For the 4 experimental data with 17 cycle times, the proposed algorithm can be obtain the minimum number of workstations m^* and can be reduce the cycle time to T_max < c then metaheuristic methods. Also, proposed clustering algorithm maximizes the line efficiency and minimizes the variance between workers operation times.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.22 no.3
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• pp.37-42
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• 2022

A high-performance wideband transition from microstrip to waveguide is proposed. This transition is designed by consideration of gradual field transformation and optimal impedance matching between microstrip line and fin-line. Clear design guidelines of proposed transition using fin-line taper with offset DSPSL (double-sided parallel stripline) are provided to determine the transition shape and the transition length. The fabricated transition exhibits less than 0.67 dB insertion loss per transition for frequencies from 85 to 108 GHz, and less than 1 dB insertion loss from 83 to over 110 GHz. Proposed transition is expected compact radar and various applications.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.23 no.2
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• pp.73-78
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• 2023

The dining philosophers problem(DPP) is that five philosophers sit around a round table and eat spaghetti(or noodles) together, where they must have a pair of chopsticks(two) on both sides of them to eat, and if all philosophers have one chopstick on the right, no one can eat because the deadlock occurs. Deadlocks are a problem that frequently occur in parallel systems, and most current operating systems(OS) cannot prevent it. This paper proposes a silver bullet that causes no deadlock in an OS where all processors of 2≤n≤∞ have multiple parallel processing capabilities. The proposed method is a group round-robin method in which ⌊n/2⌋ odd processors form a group and perform simultaneously, and shift right to the next processor when execution ends. The proposed method is to perform two times for even processors, three times for odd processors per one round-robin. If the proposed method is performed n times, even-numbered processors perform n/2 times and odd-numbered processors perform (n-1)/2-times.

• KIPS Transactions on Computer and Communication Systems
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• v.11 no.6
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• pp.167-174
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• 2022

PIPO lightweight block ciphers were announced in ICISC'20. In this paper, a single-block optimization implementation and parallel optimization implementation of PIPO lightweight block cipher ECB, CBC, and CTR operation modes are performed on a 32-bit RISC-V processor. A single block implementation proposes an efficient 8-bit unit of Rlayer function implementation on a 32-bit register. In a parallel implementation, internal alignment of registers for parallel implementation is performed, and a method for four different blocks to perform Rlayer function operations on one register is described. In addition, since it is difficult to apply the parallel implementation technique to the encryption process in the parallel implementation of the CBC operation mode, it is proposed to apply the parallel implementation technique in the decryption process. In parallel implementation of the CTR operation mode, an extended initialization vector is used to propose a register internal alignment omission technique. This paper shows that the parallel implementation technique is applicable to several block cipher operation modes. As a result, it is confirmed that the performance improvement is 1.7 times in a single-block implementation and 1.89 times in a parallel implementation compared to the performance of the existing research implementation that includes the key schedule process in the ECB operation mode.