• Journal of the Korea Academia-Industrial cooperation Society
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• v.11 no.2
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• pp.469-475
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• 2010

The railway signalling system plays an essential role in the safe and efficient train operation as serving control functions of train operation intervals and train routes. The reliability and safety of the system are very important because the failure of the railway signalling system can lead to train collision or derailment as well as train operation stop. Until now, in railway signalling system the conventional wayside signal mode has been used generally. There are, however, the risk of accidents such as human mistakes caused by that the driver identifies the signal lamp status and controls train speed with the naked eye. It is also necessary to refurbish the obsolete system. Thereby, It is being effective that the onboard signal mode has been recently introduced and applied in order to transmit the speed control information to train by using the computer and communication equipment. It is necessary to switch over the system in a way while providing passengers with an operation service to replace the obsolete signal system. In this paper, we verify the cases through trial assessment which are solved by the way of adding specific functionalities in the problems of interference among the procedure of switch-over processes and a serial of processes for system verification while a train is operated in the new system in parallel to the existing system.

• Journal of KIISE:Computing Practices and Letters
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• v.13 no.5
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• pp.252-259
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• 2007

With the rapid development of multimedia applications and wireless communication networks, consumer demand for video-over-wireless capability on mobile computing systems is growing rapidly. In this regard, this paper introduces YUV-aware instructions that enhance the performance and efficiency in the processing of color image and video. Traditional multimedia extensions (e.g., MMX, SSE, VIS, and AltiVec) depend solely on generic subword parallelism whereas the proposed YUV-aware instructions support parallel operations on two-packed 16-bit YUV (6-bit Y, 5-bits U, V) values in a 32-bit datapath architecture, providing greater concurrency and efficiency for color image and video processing. Moreover, the ability to reduce data format size reduces system cost. Experiment results on a representative dynamically scheduled embedded superscalar processor show that YUV-aware instructions achieve an average speedup of 3.9x over the baseline superscalar performance. This is in contrast to MMX (a representative Intel#s multimedia extension), which achieves a speedup of only 2.1x over the same baseline superscalar processor. In addition, YUV-aware instructions outperform MMX instructions in energy reduction (75.8% reduction with YUV-aware instructions, but only 54.8% reduction with MMX instructions over the baseline).

• Journal of KIISE:Computer Systems and Theory
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• v.35 no.9_10
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• pp.429-440
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• 2008

As embedded system becomes more complex, software development becomes more important in the entire design process. Most embedded applications consist of multi -tasks, that are executed in parallel. So, dataflow model that expresses concurrency naturally is preferred than sequential programming language to develop multitask software. For the execution of multitasking codes, operating system is essential to schedule multi-tasks and to deal with the communication between tasks. But, it is needed to execute multitasking code without as when the target hardware platform cannot execute as or target platforms are candidates of design space exploration, because it is very costly to port as for all candidate platforms of DSE. For this reason, we propose the serialized multitasking code generation technique from dataflow specification. In the proposed technique, a task is specified with dataflow model, and generated as a C code. Code generation consists of two steps: First, a block in a task is generated as a separate function. Second, generated functions are scheduled by a multitasking scheduler that is also generated automatically. To make it easy to write customized scheduler manually, the data structure and information of each task are defined. With the preliminary experiment of DivX player, it is confirmed that the generated code from the proposed framework is efficiently and correctly executed on the target system.

• Journal of Distribution Science
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• v.9 no.2
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• pp.13-24
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• 2011

With the increasing market share of retailer brands, many authors have paid considerable attention to retailer brands. Before market liberalisation in 1996 in Korea, retailer brand market was led by the supermarket retailing format, although the first retailer brand product was developed by the department store format. In parallel with the entry of foreign multiple retailers, the retailer brand market has experienced rapid growth. Particularly, the expansion of Tesco UK with well-established retailing know-how into Korea has encouraged Tesco Korea to actively get involved in retailer brand program. As a result, Tesco Korea has led retailer brand market in the Korean marketplace. The research starts with the question of why Tesco Korea has achieved such a higher retailer brand share. Accordingly, this study is to explore how Tesco UK has transferred its own retailing knowledge into Tesco Korea, in terms of retailer brand program development. In order to explore why the retailer brand share of Tesco Korea is higher than that of its counterparts, the author adopted in-depth interview with prepared-questions and store observation as a research methodology. To examine working process as well as information flows within Tesco Korea and from UK to Korea, in-depth interview method is one of the most suitable research methodologies, because of the difficulty of quantifying information or data related to work flows. In addition, to increase the validity of information, the researcher had interviews with Tesco Korea supplier and store personnel. Based on these research techniques, this research explored how Tesco UK has influenced or advised Tesco Korea, particularly, from the point of view of knowledge transfer. Since the entry of Tesco UK into Korea as a joint-venture, the retailer brand market share of Tesco Korea has continuously increased. It would be expected that Tesco UK has helped Tesco Korea to settle down in the Korean market. During interviews with Tesco and a Tesco supplier, the researcher found that Tesco Korea has obviously taken an advantage of retailing know-how created by Tesco UK. Furthermore, the retailer brand development and handling process of Tesco Korea has been operated with the help of Tesco UK. This might mean that Tesco UK has directly or indirectly an impact on the improvement of Korean retailer brand development skills. As a mechanism to transfer retailing knowledge developed in the home market into the host market, one of the international retailers, Tesco UK has adopted many different ways such as annual meeting, trading meeting to import or export own retailer brand products, offering of operation manual developed by Tesco UK and buyer cooperation between Tesco UK and Korea, in order to share information. Through these communication techniques, the knowledge of Tesco UK has been transferred to Tesco Korea. This research accordingly suggests that retailer brand market share is apparently related to how sophisticated or advanced the knowledge of the retailer brand development and handling process of retailers are. It is also demonstrated by this research that advanced development and handling skills make a considerable contribution to increasing retailer brand share in markets with a lower share or no presence of retailer brands.

• The Journal of Society for e-Business Studies
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• v.18 no.4
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• pp.45-65
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• 2013

A design file can get larger in size as the complexity of the target object increases. A large design file may reside in a large parallel computing system, such as cloud computing systems, and many designers may work concurrently on the same design file. In such a case, it is obvious that we need some kind of protection mechanism so that each user can access only the area of the file he or she is entitled to. Two approaches can be taken for this problem: one is the traditional access control mechanisms and the other encryption techniques. We take the latter approach to ensure the safety of the file even in public domain such as clouding systems, and in this paper, we suggest an encryption scheme for a file where the file is encrypted in multi-layer so that each user is allowed to access the file only at the layer for which the user has the proper access right. Each layer of the file is encrypted with different keys and these keys are exposed only to those who have the right access permit. The paper explains the necessary file format to achieve this goal and discusses the file manipulation functions to handle this new file format.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.8
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• pp.30-37
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• 2007

An exponentiation in $GF(2^m)$ is a basic operation for several algorithms used in cryptography, digital signal processing, error-correction code and so on. Existing hardware implementations for the exponentiation operation organize by Right-to-Left method since a merit of parallel circuit. Our paper proposes a polynomial exponentiation structure with a trinomial that is organized by Left-to-Right method and that utilizes a weakly dual basis. The basic idea of our method is to decrease time delay using precomputation tables because one of two inputs in the Left-to-Right method is fixed. Since $T_{sqr}$ (squarer time delay) + $T_{mul}$(multiplier time delay) of ow method is smaller than $T_{mul}$ of existing methods, our method reduces time delays of existing Left-to-Right and Right-to-Left methods by each 17%, 10% for $x^m+x+1$ (irreducible polynomial), by each 21%, 9% $x^m+x^k+1(1, by each 15%, 1% for $x^m+x^{m/2}+1$.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.1A
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• pp.93-98
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• 2004

Serial ATA interface Is inexpensive comparatively and performance is superior. So it is suitable technology in demand that now require data transmission and throughput of high speed. This paper describes a design and implementation of Serial ATA Link layer about error detection and 8b/10b encoder/decoder for DC balance in frequency 150MHz. The 8b/10b Encoder is partitioned into a 5b/6b plus a 3b/4b coder. The logical model of the block is described by using Verilog HDL at register transistor level and the verified HDL is synthesized using standard cell libraries. And it is fabricated with $0.35{\mu}m$ Standard CMOS Cell library and the chip size is about $1500{\mu}m\;*\;1500{\mu}m$. The function of this chip has been verified and tested using testboard with FPGA equipment and IDEC ATS2 test equipment. It is used to frequency of 100MHz in verification processes and supply voltage 3.3V. The result of testing is well on the system clock 100MHz. The designed and verified each blocks may be used IP in the field of high speed serial data communication.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.12
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• pp.3235-3245
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• 1996

A DDFS(Direct Digital Frequency Synthesizer) used in spread spectrum communication systems must need fast switching speed, high resolution(the step size of the synthesizer), small size and low power. The chip has been designed with four parallel sine look-up table to achieve four times throughput of a single DDFS. To achieve a high processing speed DDFS chip, a 24-bit pipelined CMOS technique has been applied to the phase accumulator design. To reduce the size of the ROM, each sine ROM of the DDFS is stored 0-.pi./2 sine wave data by taking advantage of the fact that only one quadrant of the sine needs to be stored, since the sine the sine has symmetric property. And the 8 bit of phase accumulator's output are used as ROM addresses, and the 2 MSBs control the quadrants to synthesis the sine wave. To compensate the spectrum purity ty phase truncation, the DDFS use a noise shaper that structure like a phase accumlator. The system input clock is divided clock, 1/2*clock, and 1/4*clock. and the system use a low frequency(1/4*clock) except MUX block, so reduce the power consumption. A 107MHz DDFS(Direct Digital Frequency Synthesizer) implemented using 0.8.mu.m CMOS gate array technologies is presented. The synthesizer covers a bandwidth from DC to 26.5MHz in steps of 1.48Hz with a switching speed of 0.5.mu.s and a turing latency of 55 clock cycles. The DDFS synthesizes 10 bit sine waveforms with a spectral purity of -65dBc. Power consumption is 276.5mW at 40MHz and 5V.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.3
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• pp.59-67
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• 2013

Reed-Solomon (RS) codes are powerful error-correcting codes used in diverse applications. Recently, algebraic soft-decision decoding algorithm for RS codes that can correct the errors beyond the error correcting bound has been proposed. The algorithm requires very intensive computations for interpolation, therefore an efficient VLSI architecture, which is realizable in hardware with a moderate hardware complexity, is mandatory for various applications. In this paper, we propose an efficient architecture with low hardware complexity for interpolation in soft-decision list decoding of Reed-Solomon codes. The proposed architecture processes the candidate polynomial in such a way that the terms of X degrees are processed in serial and the terms of Y degrees are processed in parallel. The processing order of candidate polynomials adaptively changes to increase the efficiency of memory access for coefficients; this minimizes the internal registers and the number of memory accesses and simplifies the memory structure by combining and storing data in memory. Also, the proposed architecture shows high hardware efficiency, since each module is balanced in terms of latency and the modules are maximally overlapped in schedule. The proposed interpolation architecture for the (255, 239) RS list decoder is designed and synthesized using the DongbuHitek $0.18{\mu}m$ standard cell library, the number of gate counts is 25.1K and the maximum operating frequency is 200 MHz.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.5
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• pp.486-492
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• 2004

In this paper, we newly propose the binary CA-CDMA(constant amplitude CDMA) system using pre-coding method to solve the high PAPR problem caused by multi-user signal transmission in the CDMA system. 4-user CA-CDMA, the basis of proposed binary CA-CDMA system, makes binary output signal for 4 input users. It produces the output of binary(${\pm}$2) amplitude by using a parity signal resulting from the XOR operation of 4 users data. Another sub-channel or more bandwidth is not necessary because it is transmitted together with user data and can be easily recovered in the receiver. The extension of the number of users can be possible by the simple repetition of the basic binary 4-user CA-CDMA. For example, binary 16-user CA-CDMA is made easily by allocating the four 4-user CA-CDMA systems in parallel and leading the four outputs to the fifth 4-user CA-CDMA system as input, because the output signal of each 4-user CA-CDMA is also binary. By the same extension procedure, binary 64 and 256-user CA-CDMA systems can be made with the constant amplitude. As a result, the code rate of this proposed CA-CDMA system is just 1 and binary CA-CDMA does not change the transmission rate with the constant output signal(PAPR = 0 ㏈). Therefore, the power efficiency of the HPA can be maximized without the nonlinear distortion. From the simulation results, it is verified that the conventional CDMA system has multi-level output signal, but the proposed binary CA-CDMA system always produces binary output. And it is also found that the BER of conventional CDMA system is increased by nonlinear HPA, but the BER of proposed binary CA-CDMA system is not changed.