• 제목/요약/키워드: Parallel Calculation

검색결과 356건 처리시간 0.025초

병력구조 전산기를 이용한 최단 경로 계산 (Shortest Path Calculation Using Parallel Processor System)

  • 서창진;이장규
    • 대한전기학회논문지
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    • 제34권6호
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    • pp.230-237
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    • 1985
  • Shortest path calculations for a large-scale network have to be performed using a decomposition techniqre, since the calculations require large memory size which increases by the square of the number of vertices in the network. Also, the calculation time increases by the cube of the number of vertices in the network. In the decomposition technique,the network is broken into a number of smaller size subnetworks for each of which shortest paths are computed. A union of the solutions provides the solution of the original network. In all of the decomposition algirithms developed up to now, boundary vertices which divide all the subnetworks have to be included in computing shortest paths for each subnetwork. In this paper, an improved algorithm is developed to reduce the number of boundary vertices to be engaged. In the algorithm, only those boundary vertices that are directly connected to the subnetwork are engaged. The algorithm is suitable for an application to real time computation using a parallel processor system which consists of a number of micro-computers or prcessors. The algorithm has been applied to a 39- vertex network and a 232-vertex network. The results show that it is efficient and has better performance than any other algorithms. A parallel processor system has been built employing an MZ-80 micro-computer and two Z-80 microprocessor kits. The former is used as a master processor and the latter as slave processors. The algorithm is embedded into the system and proven effective for real-time shortest path computations.

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CFDS 코드의 효율성 개선 (Efficiency Enhancement of CFDS Code)

  • 김재관;이정일;김종암;홍승규;이황섭;안창수
    • 한국전산유체공학회:학술대회논문집
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    • 한국전산유체공학회 2005년도 춘계 학술대회논문집
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    • pp.123-127
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    • 2005
  • The numerical analyses of the complicated flows are widely attempted in these days. Because of the enormous demanding memory and calculation time, parallel processing is used for these problems. In order to obtain calculation efficiency, it is important to choose proper domain decomposition technique and numerical algorithm. In this research we enhanced the efficiency of the CFDS code developed by ADD, using parallel computation and newly developed numerical algorithms. For the huge amount of data transfer between blocks non-blocking method is used, and newly developed data transfer algorithm is used for non-aligned block interface. Recently developed RoeM scheme is adpoted as a spatial difference method, and AF-ADI and LU-SGS methods are used as a time integration method to enhance the convergence of the code. Analyses of the flows around the ONERA M6 wing and the high angle of attack missile configuration are performed to show the efficiency improvement.

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배전선로가 초고속통신망에 미치는 유도장해 요소 분석 (A Review of Methods for Calculation of Induced Voltage to a Communication Line from Distribution Power Line)

  • 임용훈;현덕화
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2002년도 하계학술대회 논문집 C
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    • pp.1956-1958
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    • 2002
  • This paper reviews the calculation of induced voltage to a communication line from Power Transmission Line. Power lines, both overhead and underground, often run parallel to weak current lines, such as telecommunication, signal or data transmission systems or protection circuits. The coexistence of both systems in parallel over long lengths is accompanied by the possible induction of significant longitudinal voltage in the weak current line. In order to evaluate a precise induced voltage, this paper indicated problem about coefficient and numerical formula and present some induced voltage production technology standard application.

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이산화탄소를 이용한 냉동·냉장 시스템의 성능연구 (Performance of Carbon Dioxide System for Freezing and Refrigeration)

  • 김윤섭;윤린
    • 설비공학논문집
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    • 제27권2호
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    • pp.81-86
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    • 2015
  • Performance of freezing and refrigeration systems in supermarket, which utilized $CO_2$ as a refrigerant, was investigated by using the Pack Calculation II. The configuration of simulated systems was basic parallel refrigeration system, cascade system, and two-stage system. The $CO_2$ cascade system showed higher COP than basic parallel R404A system by 13% for MT and 62% for LT, respectively. Among the $CO_2$ cascade systems, R717(MT)-$CO_2$(LT) showed the highest performance. Open-type intercooler method showed higher performance than liquid injection for the two-stage $CO_2$ systems.

병렬 연산을 이용한 축류 블레이드의 역설계 (The Inverse Design Technique of Axial Blade Using the Parallel Calculation)

  • 조장근;안재성;박원규
    • 유체기계공업학회:학술대회논문집
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    • 유체기계공업학회 1999년도 유체기계 연구개발 발표회 논문집
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    • pp.200-207
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    • 1999
  • An efficient inverse design technique based on the MGM (Modified Garabedian-McFadden) method has been developed. The 2-D Navier-Stokes equations are solved for obtaining the surface pressure distributions and coupled with the MGM method to perform the inverse design. The solver is parallelized by using the domain decomposition method and the standard MPI library for communications between the processors. The MGM method is a residual-correction technique, in which the residuals are the difference between the desired and the computed pressure distribution. The developed code was applied to several airfoil shapes and the axial blade. It has been found that they are well converged to their target pressure distribution.

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실사기반 디지털 홀로그래픽 비디오의 실시간 생성을 위한 하드웨어의 설계 (A New Hardware Design for Generating Digital Holographic Video based on Natural Scene)

  • 이윤혁;서영호;김동욱
    • 전자공학회논문지
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    • 제49권11호
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    • pp.86-94
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    • 2012
  • 본 논문에서는 고속으로 홀로그램을 생성할 수 있는 하드웨어의 구조를 제안하고 이를 구현하였다. 제안한 하드웨어는 홀로그램 평면의 행 단위로 병렬 연산을 수행할 수 있는 구조를 가지고 있고, 한 행의 각 홀로그램 화소들이 독립적으로 연산될 수 있는 알고리즘을 이용하였다. 이러한 연산 방법을 통해서 홀로그램 생성 하드웨어서 가장 문제가 되는 메모리 접근량을 대폭 감소시킴으로써 하드웨어 처리능력의 실시간성을 대폭 향상시켰다. 제안한 하드웨어는 입력 인터페이스, 초기 파라미터 연산기, 홀로그램 화소 연산기, 라인 버퍼, 그리고 메모리 제어기로 구성된다. 제안한 하드웨어는 기존의 하드웨어와 동일한 처리 능력을 가지면서도 메모리 접근횟수는 약 20,000배 감소시킬 수 있었다. 구현한 하드웨어는 198MHz에서 안정적으로 동작할 수 있었고, 168,960개의 LUT, 153,944개의 레지스터, 그리고 19,212개의 DSP 블록을 사용하였다.

이산화된 Navier-Stokes 방정식의 영역분할법을 위한 병렬 예조건화 (Parallel Preconditioner for the Domain Decomposition Method of the Discretized Navier-Stokes Equation)

  • 최형권;유정열;강성우
    • 대한기계학회논문집B
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    • 제27권6호
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    • pp.753-765
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    • 2003
  • A finite element code for the numerical solution of the Navier-Stokes equation is parallelized by vertex-oriented domain decomposition. To accelerate the convergence of iterative solvers like conjugate gradient method, parallel block ILU, iterative block ILU, and distributed ILU methods are tested as parallel preconditioners. The effectiveness of the algorithms has been investigated when P1P1 finite element discretization is used for the parallel solution of the Navier-Stokes equation. Two-dimensional and three-dimensional Laplace equations are calculated to estimate the speedup of the preconditioners. Calculation domain is partitioned by one- and multi-dimensional partitioning methods in structured grid and by METIS library in unstructured grid. For the domain-decomposed parallel computation of the Navier-Stokes equation, we have solved three-dimensional lid-driven cavity and natural convection problems in a cube as benchmark problems using a parallelized fractional 4-step finite element method. The speedup for each parallel preconditioning method is to be compared using upto 64 processors.

장거리 병렬 송전선로용 대지 정전용량 보상에 의한 고장점 표정 알고리즘 (Fault Location Algorithm with Ground Capacitance Compensation for Long Parallel Transmission Line)

  • 박철원;김삼용;신명철
    • 전기학회논문지P
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    • 제54권4호
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    • pp.163-170
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    • 2005
  • This paper deals with an improved fault location algorithm with compensation ground capacitance through distributed parameter for a long parallel T/L. For the purpose of fault locating algorithm non-influenced by source impedance and fault resistance, the loop method was used in the system modeling analysis. This algorithm uses a positive and negative sequence of the fault current for high accuracy of fault locating calculation. Power system model of 160km and 300km long parallel T/L was simulated using EMTP software. To evaluate of the proposed algorithm, we used the several different cases 64 sampled data per cycle. The test results show that the proposed algorithm was minimized the error factor and speed of fault location estimation.

Current Sharing Control Strategy for IGBTs Connected in Parallel

  • Perez-Delgado, Raul;Velasco-Quesada, Guillermo;Roman-Lumbreras, Manuel
    • Journal of Power Electronics
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    • 제16권2호
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    • pp.769-777
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    • 2016
  • This work focuses on current sharing between punch-through insulated gate bipolar transistors (IGBTs) connected in parallel and evaluates the mechanisms that allow overall current balancing. Two different control strategies are presented. These strategies are based on the modification of transistor gate-emitter control voltage VGE by using an active gate driver circuit. The first strategy relies on the calculation of the average value of the current flowing through all parallel-connected IGBTs. The second strategy is proposed by the authors on the basis of a current cross reference control scheme. Finally, the simulation and experimental results of the application of the two current sharing control algorithms are presented.

Average Current Control for Parallel Connected Converters

  • Jassim, Bassim M.H.;Zahawi, Bashar;Atkinson, David J.
    • Journal of Power Electronics
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    • 제19권5호
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    • pp.1153-1161
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    • 2019
  • A current sharing controller is proposed in this paper for parallel-connected converters. The proposed controller is based on the calculation of the magnitudes of system current space vectors. Good current distribution between parallel converters is achieved with only one Proportional-Integral (PI) compensator. The proposed controller is analyzed and the circulating current impedance is derived for paralleled systems. The performance of the new control strategy is experimentally verified using two parallel connected converters employing Space Vector Pulse Width Modulation (SVPWM) feeding a passive RL load and a 2.2 kW three-phase induction motor load. The obtained test results show a reduction in the current imbalance ratio between the converters in the experimental setup from 53.9% to only 0.2% with the induction motor load.