• Journal of the Microelectronics and Packaging Society
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• v.7 no.4
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• pp.17-22
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• 2000

In this paper, methods to analyze wire sweep during the semiconductor chip encapsulation have been studied. The wire sweep analysis is used to analyze the deformation of bonding wires that connect the chip to the leadframe during encapsulation. The analysis is done using either analytical solutions or numerical simulation. The analytical solution is used for rough but fast calculation of wire sweep. The results from the numerical simulation are closest to the experimental results.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.7
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• pp.1418-1423
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• 2009

This paper describes the design and implementation of a System-on-a-Chip (SoC) for image processing applications to use in wearable/mobile products. The target Soc consists of LEON 2 core, AMBA/APB bus-systems and custom-designed controllers. A new FPGA-based prototyping platform is implemented and used for design and verification of the target SoC. To ensure that the implemented SoC satisfies the required performances, an image processing application is performed.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.10
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• pp.1841-1846
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• 2008

In this paper, we present the fabrication of microlens by electrohydrodynamic atomization(EHDA) of PDMS prepolymer. The diameter and contact angle of PDMS microlens can be altered by changing the applied voltage and substrate temperature at the experimental setup. It is considered that PDMS microlens can be integrated into the Lab-on-a-chip directly without any photolithographic process by EHDA. The property of PDMS microlens is confirmed by transmitting and measuring the Gaussian beam through microlens.

• Proceedings of the KSME Conference
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• 2007.05a
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• pp.1522-1525
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• 2007

Circular milling operations are used to enlarge die and cylinder bores, and machine airframe pockets. In this case, cutting force varies as cutting tool position relative to workpiece. This paper presents a mechanistic model of geometric uncut chip thickness by predicting time varying cutter-part intersection as the cutter travels along the circular path. Compared with experimental results, the suggested cutting force model shows a good agreement.

• Proceedings of the KIEE Conference
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• 1987.07b
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• pp.978-980
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• 1987

This paper presents a scheme of $16{\times}16$ VLSI crosspoint chip as a key Component in future broadband switching network operating at bit rates UP to 140Mbit/s using space division switching technique. First, functional requirements of the chip are investigated in terms of a large switching unit. Then, a regeneration circuit to provide reshaping of previsiously switched signals is presented.

• Proceedings of the KIEE Conference
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• 2005.07a
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• pp.365-367
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• 2005

This paper proposes a hardware of IED for power transformer protection that is well constructed using DSP chip and MPU chip. The performance of the adaptive relaying algorithm, by real-time testing in a prototype of it, has been verified. And test results indicate the proposed relaying of the IED was proven to be faster and more reliable.

• Journal of the Microelectronics and Packaging Society
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• v.8 no.2
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• pp.49-52
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• 2001

This paper presents product level considerations for multichip packaging as a cost effective alternative to single chip packaging in the design and manufacture of mobile telephony products. Important aspects include component functionality and complexity, acquisition and logistics costs, product modularity and integration. Multichip packaging offers unique solutions and significant system level cost savings in many applications including RF modules, digital matrix functions and product options such as security, data storage, voice recognition, etc.

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07b
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• pp.854-857
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• 2005

We developed new circuit architecture for reducing the power consumption and chip-size of driver ICs. In this paper we describe a new drive scheme, based on the concept of time -sharing output and optimal circuit design based on color resolution. In case of 132 x 176-pixel class, we used only 8 O p-A mps for a 262-k color display.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.782-785
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• 2002

Power amplifier of wireless communication tranceiver can be effectually controlled output power. And small size and low power dissipation are indispensable to portable system. In this paper, to reduce the size of portable tranceiver, inductor is integrated in a single chip. And to reduce power dissipation, a power amplifier that can be digitally controlled output power, is proposed and designed.

• Journal of the Korean Society for Precision Engineering
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• v.21 no.10
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• pp.188-195
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• 2004

In this paper, we fabricated fluidic devices like micro-channel, pump, mixer and particular gas separator with the technology of stereolithouaphy using RP(rapid-prototyping). The fabricated fluidic devices are expected to be applied to develop Lab-on-a chip type liquid analyzer. Stereolithography technology seems effective for fabricating MEMS(Micro Electro Mechanical System) with complicated structure because it makes three dimensional fabrication possible but, exclusive devices are needed to be developed fur fabricating even more microscopic MEMS structure.