• Proceedings of the Korean Society of Precision Engineering Conference
• /
• 2002.05a
• /
• pp.807-811
• /
• 2002

As the requirements on precision and speed of motion in chip mounter increase, vibration forces are always exerted on operating conditions. To insure safety of the chip mounter, the vibration must be kept within an acceptable limit. The focus of this paper is on the identification of dynamic load characteristics and the estimation of static and dynamic stiffness characteristics for Frame Base by judicious selection of the number and the location of the support points. This study carried an analytical and experimental method to estimate the dynamic characteristics in structure.

• Transactions of the Korean Society of Machine Tool Engineers
• /
• v.16 no.2
• /
• pp.30-36
• /
• 2007

In order to estimate the maximum undeformed chip thickness in grinding operation, it is necessary to obtain the successive cutting point spacing. In the past it was obtained by experiments. In this paper, the average successive cutting point spacing has been obtained using the given grinding input conditions and it is possible to estimate the maximum undeformed chip thickness without using any experimentally obtained data. The validity of the proposed analysis has been verified based on two sets of grinding scratch tests using WA and CBN grinding wheels.

• The Transactions of the Korean Institute of Electrical Engineers P
• /
• v.53 no.4
• /
• pp.166-170
• /
• 2004

In this paper, it has been proposed the simultaneous control of PFC (power factor corrector) and electronic ballast for fluorescent lamp by one chip micro-controller. Boost DC-DC converter is adopted for PFC, and half bridge inverter for electronic ballast. It controls, simultaneously and independently, the boost DC-DC converter and the half bridge inverter. As PFC and electronic ballast are controlled by one chip micro-controller, it is possible to achieve the simpler and the cheaper controller for fluorescent lamp. Experimental results have shown the feasibility of the proposed simultaneous control of PFC and electronic ballast by one chip micro-controller.

• Proceedings of the KIEE Conference
• /
• 2001.07b
• /
• pp.1055-1057
• /
• 2001

The switching circuit of PWM inverter is very complicated. By using one-chip $\mu$-com the complication of switching circuit is possible to be diminished. But because in one-chip $\mu$-com the limitation of processed memory size exists, the switching handling method has to be simple. In this paper, to effectively utilize the switching handling, we presented the estimation method of PWM pulses which is different form the conventional PWM switching method by the comparison.

• Proceedings of the KIEE Conference
• /
• 2000.07a
• /
• pp.215-217
• /
• 2000

Protective relay play a crucial role in the proper operation of a power system, and the reliable transfer of electrical power. This paper deals with the design and implementation of a digital protective relay on a single chip. Implementation on the FPGA(Field Programmable Gate Array) of the chip of digital protective relay. This protective relaying chip monitors the frequency and the voltage and current of the power system. And report the voltage, the current. the frequency, active power and reactive power.

• Journal of the Semiconductor & Display Technology
• /
• v.12 no.1
• /
• pp.53-59
• /
• 2013

Chip mounter which is used to pick chips from the pre-specified position and place them on the target location of PCB is an essential device in semiconductor and LCD industries. Quick and high precision positioning is the key technology needed to increase productivity of chip mounters. As increasing acceleration and deceleration of placing motion, structural vibration induced from inertial reactive force and flexibility of mounter structure becomes a serious problem degrading positioning accuracy. Motivated from these, this paper proposed a new control design algorithm which combines a mounter structure acceleration feedforward compensation and an extended sliding mode control for fine positioning and suppression of structural vibration, simultaneously. The feasibility of the proposed control design was verified along with some simulation results.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.27 no.8
• /
• pp.1201-1210
• /
• 1990

This paper proposes on-chip instruction and data cache memories on RISC reduced instruction set computer) architecture which supports fast instruction fetch and data read/write, and enables RISC processor under research to obtain high performance. In the execution of HLL(high level language) programs, heavily used local scalar variables are stored in large register file, but arrays, structures, and global scalar variables are difficult for compiler to allocate registers. These problems can be solved by on-chip Instruction/Data cache. And each cycle of instruction fetch, pad delay causes the lowering of the processors's performance. Cache memories are designed in CMOS technology and SRAM(static-RAM), that saves layout area and power dissipation, is used for instruction and data storage. To speed up and support RISC processor's piplined architecture efficiently, hardwired logic technology is used overall circuits i cache blocks. The schematic capture and timing simulation of proposed cache memorises are performed on Apollo DN4000 workstation using Mentor Graphics CAD tools.

• Proceedings of the Korea Information Assurance Society Conference
• /
• 2004.05a
• /
• pp.59-64
• /
• 2004

In this paper a design and an implementation of a crypto chip which implements SEED and Triple-DES algorithms are described. We designed it by VHDL(VHSIC Hardware Description Language) which is a designed system-description language. To apply the chip to various application, four operating Modes such as ECB, CBC, CFB, and CFB are supported. The chip was designed by the Virtex-E XCV2000E BG560 of Xilinx and we confirmed result of it at the FPGA implementation by functional and timing simulation using the Xilinx Foundation Series 3.li.

• Speech Sciences
• /
• v.14 no.4
• /
• pp.157-167
• /
• 2007

In this paper, we implemented a single-chip speech recognizer using the TMS320C2000 DSPs. For this implementation, we had developed very small-sized speaker-dependent recognition engine based on dynamic time warping, which is especially suited for embedded systems where the system resources are severely limited. We carried out some optimizations including speed optimization by programming time-critical functions in assembly language, and code size optimization and effective memory allocation. For the TMS320F2801 DSP which has 12Kbyte SRAM and 32Kbyte flash ROM, the recognizer developed can recognize 10 commands. For the TMS320F2808 DSP which has 36Kbyte SRAM and 128Kbyte flash ROM, it has additional capability of outputting the speech sound corresponding to the recognition result. The speech sounds for response, which are captured when the user trains commands, are encoded using ADPCM and saved on flash ROM. The single-chip recognizer needs few parts except for a DSP itself and an OP amp for amplifying microphone output and anti-aliasing. Therefore, this recognizer may play a similar role to dedicated speech recognition chips.

• Proceedings of the KIPE Conference
• /
• 1998.11a
• /
• pp.5-8
• /
• 1998

The adaptation to vector control theory is so generalized that it is widely used for implementing the high-performance of AC machine. Nowadays, One-Chip microprocessors or DSP chips are being well-used to implement Vector Control algorithm. DSP Chip have less flexibility for memory decoding and I/O rather than One-Chip microprocessor so that is requires more additional circuit and high cost. And the past One-Chip micro processors have difficult of implementation the complex algorithm because of small memory capacity and low arithmetic performance. Therefore we implemented the vector control algorithm of PMSM(Permanent Magnetic Synchronous Motors) using 80296SA form intel , which have many features as 6M memory space, 500MHz clock frequency, including memory decoding circuit and general I/O, Special I/O(EPA, Interrupt controller, Timer/Count, PWM generator) which is proper controller for the complex algorithm or operation program requiring so much memory capacity, So in this paper we fully digitized the vector control of PMSM included SVPWM Voltage controller using the intel 80296SA