• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.927-930
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• 2003

In this paper, a design of processor IP for TCP/IP protocol stack is described. The processor consists of input and output buffer memory with dual bank structure, 32-bit RISC microprocessor core, DMA unit with on-the-fly checksum capability. To handle the various modes of TCP/IP protocol, hardware and software co-design approach is used rather than the conventional state machine based design. To eliminate delay time due to the data transfer and checksum operation, DAM module which can execute the checksum operation on-the-fly along with data transfer operation is adopted. By programming the on-chip code ROM of RISC processor differently. the designed stack processor can support the packet format conversion operations required in the various TCP/IP protocols.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.2
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• pp.1-7
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• 1996

In this paper, we analyzed the packet blocking probability of a finite buffer in a network interface unit. In general, a network interface unit which provides a means of interface between the network and computer has a microprocessor and a protocol processor for the network access protocols. It also has a receive buffer for the arriving packets from the network which is served by the microprocessor with service interruption by the protocol processor. In this paper, we modeled the receive buffer as a discrete time server with service interruption, and obtained the packet blocking probability using the mini-slot approximation.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.2 no.1 s.2
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• pp.93-100
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• 2003

In this farer, An ADSRC(Advanced Dedicated Short Range Communication) packet communication system developed by ETRI is introduced. The ADSRC system has been developed to provide high-speed, short-range wireless racket communication in roadside environment for mobile office services. The requirements of the ADSRC system for mobile office services and the system design specification to meet them with regard to mobile of nce environment are discussed. The ADSRC packet communication systems consist of the MAC(Medium Access Control) Processor block the OFDM() modem block and the RF block. The MAC processor block handles medium access control. The OFDM modem transmits data packets at up to 24Mbps adaptively and recovers the data from RF block. The ADSRC packet communication system architecture is described.

• Journal of KIISE:Information Networking
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• v.31 no.4
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• pp.363-374
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• 2004

In this paper, we propose an in-line mode NIDS using network processors(NPs) that achieve performance comparable to ASIC and flexibility comparable to general-purpose processors. Even if many networking applications using NPs have been proposed, we cannot find any NP applications to NIDS in the literature. The proposed NIDS supports packet payload inspection detecting attacks, as well as packet filtering and traffic metering. In particular, we separate the filtering and metering functions from the complicated and time-consuming operations of the deep packet inspection function using two-level searching scheme, thus we can improve the performance, stability, and scalability of In-line mode system. We also implement a proto-type based on a PC platform and the Agere PayloadPlus (APP) 2.5G NP solution, and present a payload inspection algorithm to apply APP NP.

• The KIPS Transactions:PartC
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• v.10C no.1
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• pp.71-76
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• 2003

Internet traffic is getting tremendously heavier due to the exponential growth of the Internet users, the spread of the E-commerce and the network games. High-speed routers for fast packet forwarding are commercially available to satisfy the growing bandwidth. A high-speed router, which has the decentralized multiprocessing architecture for IP and routing functions, consists of host processors, line interfaces and switch fabrics. In this paper, we propose a software architecture tuned for high-speed non-forwarding packet manipulation. IPCMP (Inter-Processor Communication Message Protocol), which is a mechanism for IPC (Inter-Processor Communication), is also proposed and implemented as well. Proposed IPC mechanism results in faster packet-processing rate by 10% as compared to the conventional IPC mechanism using UDP/IP.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.40 no.10
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• pp.79-88
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• 2003

We demonstrate a novel all-optical packet switching system that is suitable for optical ring networks. For the demonstration, video signals are encoded into optical packets which are composed of header and payload. The optical packets are all-optically processed at a switching node based on all-optical header processor, packet-level clock extraction, bit-level clock extraction, all-optical data format converter and so on.

• Proceedings of the KIEE Conference
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• 2006.10c
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• pp.397-400
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• 2006

Recent trend on high speed packet processing for providing multiple internet services is to use network processor instead of being implemented by legacy ASIC or FPGA. Most frequently used network processor interface is the SPI4.2. This paper address the data-rate conversion interface device between SPI4.2 and SPI3/CSIX, implemented using XILINX XC2VP40 FPGA. Furthermore, we address the methodology and necessity of flow control occurred due to the data rate difference between 10Gbps and 3.2 Gbps.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.53 no.6
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• pp.440-445
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• 2004

The design and implementation of a Network Processor using System-on-a-chip(SoC) technology is presented. The proposed network processor can handle several protocols as well as various types of traffics simultaneously. The proposed SoC consists of ARM processor core, ATM block, AAL processing block, Ethernet block and a scheduler. The scheduler guarantees QoS of the voice traffic and supports multiple AAL2 packet. The SoC is manufactured on the 0.35 micron fabrication line of HYNIX semiconductor, the total number of gates is about 312,000, for a maximum operating frequency of over to 50㎒.

• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.4
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• pp.167-174
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• 2003

This paper proposes a network processor especially optimized for content switching. With 2Gbps port capability, it integrates packet processor cluster, content-based classification engine and traffic manager on a single chip. A switch fabric architecture is also designed for scale-up of the network processor's capability over hundreds gigabit bandwidth. Applied in real network systems, the network processor shows wire-speed network address translator (NAT) and content-based switching performance.

• Journal of Korea Multimedia Society
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• v.10 no.12
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• pp.1622-1631
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• 2007

To realize the wireless packet scheduler which efficiently considers both the effect of adaptive modulation and coding (AMC) scheme due to variable wireless communication channel information from physical layer and the QoS differentiation of multimedia services from internet protocol (IP) layer, this paper proposes a new downlink AMC-based priority queuing (APQ) scheduler which combines AMC scheme and service priority method in multimedia services at the same time. The result of numerical analysis shows that the proposed APQ algorithm plays a role in increasing the number of services satisfying the mean waiting time requirements per each service in multimedia services because the APQ scheme allows the mean waiting time of each service to be reduced much more than existing packet scheduler having only user selection processor.