• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.101-104
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• 2001

In this paper, we have analyzed algorithm about physical layer, data link layer and MAC layer of out-of-band specified in the DVS 178 and designed architecture of Out-of-band processor. Out-of-band processor extracts session key information from EMM packet to descramble MPEG-2 TS packet scrambled. Also, analyze EAS Packet including emergency alert information to provide emergency communications such as national emergency. In this paper, we have implemented prototype board for out-of-band processor.

• Journal of Korean Institute of Industrial Engineers
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• v.40 no.1
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• pp.135-139
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• 2014

In a connection-oriented packet switching network, the data communication starts after a virtual circuit is established between source and destination. The virtual circuit establishment time includes the queue waiting times in the direction from source to destination and the other way around. We use this two-way queueing delay to evaluate scheduling policies of a packet switching processor through simulation studies. In this letter, we also suggest user testing functions for the packet switching processor to manage virtual circuits. By detecting error causes, the user testing helps the packet switching processor provide reliable connection-oriented services.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.7
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• pp.63-73
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• 2004

This paper proposes an efficient centralized sin91e buffer management algorithm to arbitrate access contention mon processors on the multi-processor system for high-speed Packet filtering and proves that the algorithm provides reasonable performance by implementing it and applying it to a real multi-processor system. The multi-processor system for parallel packet filtering is modeled based on a network processor to distribute the packet filtering rules throughout the processors to speed up the filtering. In this paper we changed the number of processors and the processing time of the filtering rules as variables and measured the packet transfer rates to investigate the performance of the proposed algorithm.

• The KIPS Transactions:PartC
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• v.16C no.4
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• pp.417-422
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• 2009

Implementation of DPI(Deep Packet Inspection) system on a general purpose multiprocessor platform is an attractive option from the implementation cost point of view, since it does not require high-cost customized hardware. Load balancing has been considered as a primary means to achieve high performance in multi processor systems. We claim, however, that in case of DPI system design simply balancing the load of each processor does not necessarily yield the highest system performance. Instead, we propose a method in which tasks are allocated to processors based on their functions. We implemented the proposed method in dual processor Linux system and compare its performance with the existing load balancing methods. Under the proposed method, one processor is dedicated to deal with interrupt handling and generic packet processing, while another processor is dedicated to DPI processing. According to experimental results, the proposed scheme outperforms the existing schemes by 60%, mainly because of the reduction of cache miss and spin lock occurrences.

• ETRI Journal
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• v.34 no.6
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• pp.827-837
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• 2012

We propose a flow admission control (FAC) for setting up a wire-speed connection for new flows based on their negotiated bandwidth. It also terminates a flow that does not have a packet transmitted within a certain period determined by the users. The FAC can be used to provide a reliable transmission of user datagram and transmission control protocol applications. If the period of flows can be set to a short time period, we can monitor active flows that carry a packet over networks during the flow period. Such powerful flow management can also be applied to security systems to detect a denial-of-service attack. We implement a network processor called a flow management network processor (FMNP), which is the second generation of the device that supports FAC. It has forty reduced instruction set computer core processors optimized for packet processing. It is fabricated in 65-nm CMOS technology and has a 40-Gbps process performance. We prove that a flow router equipped with an FMNP is better than legacy systems in terms of throughput and packet loss.

• The KIPS Transactions:PartC
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• v.12C no.1 s.97
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• pp.11-18
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• 2005

This paper proposes a packet header collector, based on a network processor with multi-processor and multi-threads, that shows a high throughput on gigabit network. The proposed collector has an architecture to separate packets coming from gigabit network into headers and payloads, and distribute them to multiple 100Mbit MAC ports. The architecture hiring a unique buffer management method and load distribution strategy among multiple processors is evaluated empirically in depth.

• Proceedings of the Optical Society of Korea Conference
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• 2002.11a
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• pp.58-59
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• 2002

Jitter noise power at the all optical packet header processor, which uses a fiber-optic delay-line matched filter, has been calculated for various optical pulse shapes.

• Proceedings of the IEEK Conference
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• summer
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• pp.39-41
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• 2004

In this paper, I propose a thread scheduling policy for faster packet processing on the network processors with multithreaded multiprocessor architecture. To implement the proposed policy, I derived several basic parameters related to the thread scheduling and included a new parameter representing the packet contents and the features of the multithreaded architecture. Through the empirical study using a network processor, I proved the proposed scheduling ploicy provides better throughput and load balancing compared to the generally used thread scheduling policy.

• Proceedings of the Optical Society of Korea Conference
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• 2000.08a
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• pp.18-19
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• 2000

In this paper, packet error rates of an all-optical packet switching node, which uses a fiber-optic delay-line matched filter as the optical packet header processor, has been calculated for the various optical pulse shapes.

• Journal of KIISE:Computing Practices and Letters
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• v.9 no.4
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• pp.447-454
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• 2003

The forwarding enging, which handles the incoming frames and forwards them to the appropriate outgoing interface, is the crucial factor of the router´s performance. As the MPLS label edge router provides the facility that it is capable of interworking with various kinds of networks, the forwarding engine should have the flexibility processing the corresponding types of frames from such network interfaces. In order to support the flexibility, we implement the forwarding engine for the MPLS LER with ATM interfaces based on the programmable Ethernet packet processor. By exploiting instinct loop-back functionality of Ethernet packet processor, our forwarding engine handles and forwards the frames from/to ATM interfaces. The performance of our forwarding engine is evaluated by experiments on the effect of looping frames back and the number of Ethernet packet processor´s instructions.