• Journal of Advanced Marine Engineering and Technology
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• 제33권1호
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• pp.131-137
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• 2009

In this paper, we have manufactured hole type PRAM unit cell using phase change material $Ge_2Sb_2Te_5$. The phase change material $Ge_2Sb_2Te_5$ was deposited on hole of 500 nm size using sputtering method. Reset current of PRAM unit cell was confirmed by measuring R-V characteristic curve. Reset current of manufactured hole type PRAM unit cell is 15 mA, 100 ns. And electro and thermal characteristics of hole type PRAM unit cell were analyzed by 3-D finite element analysis. From simulation temperature of PRAM unit cell was $705^{\circ}C$.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2003년도 추계학술발표강연 및 논문개요집
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• pp.179-179
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• 2003

현재 차세대 메모리로 연구되고 있는 것 중 가장 각광 받는 것은 PRAM 이다. MRAM의 경우 복잡한 공정 때문에 상용화에 많은 어려움이 따르는데 반해 PRAM은 DRAM과 유사한 구조를 가지고 있기 때문에 기존 DRAM의 공정라인을 사용할 수 있다는 장점을 가지고 있다. 하지만 PRAM은 높은 작동전류가 필요하다는 단점을 가지고 있다. 따라서 PRAM이 상용화 되기 위해서는 2mA 이하의 작동전류에서 상변환이 일어나야 한다. 여기서 말하는 상변환이란 결정질 상태를 비정질 상태로 변환 시키는 것을 의미한다. 본 연구에서는 우선 8F$^2$ 크기(F=0.15$\mu\textrm{m}$)의 DRAM 단위소자 메모리 구조를 이용하여 lT/lRPCRAM 모델을 구축하였다. 구축된 모델을 이용하여 요구되는 작동전류(2mA이하)에서의 PRAM의 온도 분포를 시뮬레이션을 통하여 예측하였다. 또한 단위소자를 구성하는 재료의 물성 변화가 소자 내부의 온도 분포에 미치는 영향을 분석하였다.

• 대한임베디드공학회논문지
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• 제11권4호
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• pp.209-218
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• 2016

This paper proposes a new lifetime aware buffer mapping method of a synchronous dataflow (SDF) graph on a hybrid memory system with DRAM and PRAM. Since the number of write operations on PRAM is limited, the number of written samples on PRAM is minimized to maximize the lifetime of PRAM. We improve the utilization of DRAM by mapping more buffers on DRAM through buffer sharing. The problem is formulated formally and solved by an optimal approach of an answer set programming. In experiment, the buffer mapping method with buffer sharing improves the PRAM lifetime by 63%.

• JSTS:Journal of Semiconductor Technology and Science
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• 제8권2호
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• pp.128-133
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• 2008

Phase-change random access memory (PRAM) chip cell phase of amorphous state is rapidly changed to crystal state above 160 Celsius degree within several seconds during Infrared (IR) reflow. Thus, on-board programming method is considered for PRAM chip programming. We demonstrated the functional 512Mb PRAM with 90nm technology using several novel core circuits, such as metal-2 line based global row decoding scheme, PN-diode cells based BL discharge (BLDIS) scheme, and PMOS switch based column decoding scheme. The reverse-state standby current of each PRAM cell is near 10 pA range. The total leak current of 512Mb PRAM chip in standby mode on discharging state can be more than 5 mA. Thus in the proposed BLDIS control, all bitlines (BLs) are in floating state in standby mode, then in active mode, the activated BLs are discharged to low level in the early timing of the active period by the short pulse BLDIS control timing operation. In the conventional sense amplifier, the simultaneous switching activation timing operation invokes the large coupling noise between the VSAREF node and the inner amplification nodes of the sense amplifiers. The coupling noise at VSAREF degrades the sensing voltage margin of the conventional sense amplifier. The merit of the proposed sense amplifier is almost removing the coupling noise at VSAREF from sharing with other sense amplifiers.

• 한국정보과학회논문지:시스템및이론
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• 제26권10호
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• pp.1258-1263
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• 1999

본 논문에서는 CRCW(Concurrent Read Concurrent Write)와 CREW(Concurrent Read Exclusive Write) PRAM(Parallel Random Access Machine) 모델에서 무방향성 그래프 G=(V, E)의 극대 매칭을 구하기 위해 간결한 랜덤 병렬 알고리즘을 제안한다. CRCW PRAM 모델에서 m개의 선을 가진 그래프에 대해, 제안된 매칭 알고리즘은 m개의 프로세서 상에서 {{{{ OMICRON (log m)의 기대 수행 시간을 가진다. 또한 CRCW 알고리즘을 CREW PRAM 모델에서 구현한 CREW 알고리즘은 OMICRON (log^2 m)의 기대 수행 시간을 가지지만,OMICRON (m/logm) 개의 프로세서만을 가지고 수행될 수 있다.Abstract This paper presents simple randomized parallel algorithms for finding a maximal matching in an undirected graph G=(V, E) for the CRCW and CREW PRAM models. The algorithm for the CRCW model has {{{{ OMICRON (log m) expected running time using m processors, where m is the number of edges in G We also show that the CRCW algorithm can be implemented on a CREW PRAM. The CREW algorithm runs in {{{{ OMICRON (log^2 m) expected time, but it requires only OMICRON (m / log m) processors.

• Journal of applied mathematics & informatics
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• 제19권1_2호
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• pp.77-92
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• 2005

An efficient parallel algorithm is presented to find a maximum weight independent set of a permutation graph which takes O(log n) time using O($n^2$/ log n) processors on an EREW PRAM, provided the graph has at most O(n) maximal independent sets. The best known parallel algorithm takes O($log^2n$) time and O($n^3/log\;n$) processors on a CREW PRAM.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 하계학술대회 논문집 Vol.8
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• pp.144-145
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• 2007

Phase change random access memory is one of the most promising candidates for next generation non-volatile memories. However, the high reset current is one major obstacle to develop a high density PRAM. One way of the reset current reduction is to develop the new phase change material. In this paper, to reduce the reset current for phase transition, we have investigated the effect of phase change material parameters using finite element analysis.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 추계학술대회 논문집
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• pp.97-98
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• 2007

In this paper, we analyzed the reset current variation of PRAM device with top electrode using the 3-D finite element analysis tool. As thickness of phase change material thin film decreased, reset current caused by phase transition highly increased. Joule's heat which was generated at the contact surface of phase change material and bottom electrode of PRAM was given off through top electrode to which was transferred phase change material. As thermal conductivity of top electrode decreased, heating temperate was increased.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2005년도 하계학술대회 논문집 Vol.6
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• pp.205-206
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• 2005

PRAM (Phase change Random Access Memory) is one of the most promising candidates for next generation Non-volatile Memories. The Phase change material has been researched in the field of optical data storage media. Among the phase change materials, $Ge_2Sb_2Te_5$(GST) is very well known for its high optical contrast in the state of amorphous and crystalline. However, the characteristics required in solid state memory are quite different from optical ones. In this study, the structural properties of GST thin films with bottom electrode were investigated for PRAM. The 100-nm thick GST films were deposited on TiN/Si and TiAlN/Si substrates by RF sputtering system. In order to characterize the crystal structure and morphology of these films, we performed x-ray diffraction (XRD) and atomic force microscopy (AFM).

• 전자공학회지
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• 제32권10호
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• pp.65-70
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• 2005

강 유전체 메모리(FRAM)와 상 변화 메모리(PRAM)는 기존의 메모리들이 갖고 있는 문제점들을 해결할 수 있는 이상적인 메모리로 주목 받고 있다. 현재 FRAM과 PRAM을 구현하는데 있어서 가장 큰 어려움은 셀의 크기와 대용량이다. 따라서 신 메모리의 셀 크기를 결정짓는 중요 요소들과 이를 해결할 수 있는 공정 기술들에 대하여 살펴보았다.