• Journal of Power Electronics
• /
• v.18 no.3
• /
• pp.863-870
• /
• 2018

The traditional power control theories for the harmonic reduction methods in multilevel inverters are found to be unreliable under unbalanced load conditions. The unreliability in harmonic mitigation is caused by voltage fluctuations, non-linear loads, the use of power switches, etc. In general, the harmonics are reduced by filters. However, such devices are an expensive way to provide a smooth and fast response to secure power systems during dynamic conditions. Hence, the Decoupled Double Synchronous Reference Frame (DDSRF) theory combined with a State Delay Controller (SDC) is proposed to achieve a harmonic reduction in power systems. The DDSRF produces a sinusoidal harmonic that is the opposite of the load harmonic. Then, it injects this harmonic into power systems, which reduces the effect of harmonics. The SDC is used to reduce the delay between the compensation time for power injection and the generation of a reference signal. The proposed technique has been simulated using MATLAB and its reliability has been verified experimentally under unbalanced conditions.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.58 no.5
• /
• pp.936-943
• /
• 2009

Dynamic voltage restorer(DVR) is now more preferable enhancement than other power quality enhancement in industry to reduce the impact of voltage faults, especially voltage sags to sensitive loads. The main controllers for DVR consists of PLL(phase locked loop), compensation voltage calculator and voltage compensator. PLL detects the voltage faults and phase. Compensation voltage calculator calculates the reference voltage from the source voltage and phase. With calculated compensation voltage from PLL, voltage compensator restores the source voltage. If PLL detect ideal phase, compensation voltage calculator calculates ideal compensation voltage. Therefore, PLL for DVR is very important. This paper proposes the new method of PLL in DVR. First, the power circuit of DVR system is analyzed in order to compensate the voltage sags. Based on the analysis, new PLL for improving transient response of DVR is proposed. The proposed method uses band rejection filter(BRF) at q-axis in synchronous flame. In order to calculate compensation voltage in commercial instruments, the PQR theory is used. Proposed PLL method is demonstrated through simulation using Matlab-Simulink and experiment, and by checking load voltage, confirms operation of the DVR

• Journal of Power Electronics
• /
• v.11 no.4
• /
• pp.576-582
• /
• 2011

This paper presents a novel control strategy for selective compensation of power quality (PQ) problems, depending upon the limited rating of voltage source inverters (VSIs), through a unified power quality conditioner (UPQC) in a three-phase four-wire distribution system. The UPQC is realized by the integration of series and shunt active power filters (APFs) sharing a common dc bus capacitor. The shunt APF is realized using a three-phase, four-leg voltage source inverter (VSI), while a three-leg VSI is employed for the series APF of the three-phase four-wire UPQC. The proposed control scheme for the shunt APF, decomposes the load current into harmonic components generated by consumer and distorted utility. In addition to this, the positive and negative sequence fundamental frequency active components, the reactive components and harmonic components of load currents are decomposed in synchronous reference frame (SRF). The control scheme of the shunt APF performs with priority based schemes, which respects the limited rating of the VSI. For voltage harmonic mitigation, a control scheme based on SRF theory is employed for the series APF of the UPQC. The performance of the proposed control scheme of the UPQC is validated through simulations using MATLAB software with its Simulink and Power System Block set toolboxes.