• Journal of Power Electronics
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• v.18 no.1
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• pp.234-250
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• 2018

This paper presents a new load sharing control for use between paralleled three-phase inverters in an islanded microgrid based on the online line impedance estimation by the use of a Kalman filter. In this study, the mismatch of power sharing when the line impedance changes due to temperature, frequency, significant differences in line parameters and the requirements of the Plug-and-Play mode for inverters connected to a microgrid has been solved. In addition, this paper also presents a new droop control method working with the line impedance that is different from the traditional droop algorithm when the line impedance is assumed to be pure resistance or pure inductance. In this paper, the line impedance estimation for parallel inverters uses the minimum square method combined with a Kalman filter. In addition, the secondary control loops are designed to restore the voltage amplitude and frequency of a microgrid by using a combined nominal value SOGI-PLL with a generalized integral block and phase lock loop to monitor the exact voltage magnitude and frequency phase at the PCC. A control model has been simulated in Matlab/Simulink with three voltage source inverters connected in parallel for different ratios of power sharing. The simulation results demonstrate the accuracy of the proposed control method.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.2
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• pp.152-158
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• 2004

A low phase noise frequency synthesizer at X-Band which employs the subharmonic injection locking was designed and tested. The designed frequency synthesizer consists of a 1.75 GHz master oscillator - which also operates as a harmonic generator - and a 10.5 GHz slave oscillator. A 1.75 GHz master oscillator based on PLL technique used two transistors - one constitutes the active part of VCO and the other operates as a buffer amplifier as well as harmonic generator. The first stage operates a fixed locked oscillator and using the BJT transistor whose cutoff frequency is 45 GHz, the second stage is designed, operating as a harmonic generator. The 6th harmonic which is produced from the harmonic generator is injected into the following slave oscillator which also behaves as an amplifier having about 45 dB gain. The realized frequency synthesizer has a 7.4 V/49 mA, -0.5 V/4 mA of the low DC power consumption, 4.53 dBm of output power, and a phase noise of -95.09 dBc/Hz and -108.90 dBc/Hz at the 10 kHz and 100 kHz offset frequency, respectively.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.8
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• pp.1-9
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• 2009

In this paper, we describe DSSS transceiver development robust to jamming signals as an investigation of ECCM transceiver for UAV uplink. The jamming margin is 15dB or greater with the development target of transceiver because the jamming margin is more important than the transmission rate of data and the spreading code can be changeable. The rake receiver is applied to combine multipath components and turbo code which the coding gain is 7.2dB as a FEC. In this paper, the whole structure, design method and functional test result about the designed modem are described and a conclusion is made.

• Journal of Power Electronics
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• v.18 no.5
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• pp.1523-1535
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• 2018

High-performance Phase-Locked Loops (PLLs) are critical for grid synchronization in grid-tied power electronic applications. In this paper, a new single-phase All Digital Phase-Locked Loop (ADPLL) is proposed. It features fast transient response and good robustness under distorted grid conditions. It is designed for Field Programmable Gate Array (FPGA) implementation. As a result, a high sampling frequency of 1MHz can be obtained. In addition, a new OSG is adopted to track the power frequency, improve the harmonic rejection and remove the dc offset. Unlike previous methods, it avoids extra feedback loop, which results in an enlarged system bandwidth, enhanced stability and improved dynamic performance. In this case, a new parameter optimization method with consideration of loop delay is employed to achieve a fast dynamic response and guarantee accuracy. The Phase Detector (PD) and Voltage Controlled Oscillator (VCO) are realized by a Coordinate Rotation Digital Computer (CORDIC) algorithm and a Direct Digital Synthesis (DDS) block, respectively. The whole PLL system is finally produced on a FPGA. A theoretical analysis and experiments under various distorted grid conditions, including voltage sag, phase jump, frequency step, harmonics distortion, dc offset and combined disturbances, are also presented to verify the fast dynamic response and good robustness of the ADPLL.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.4 s.334
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• pp.1-6
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• 2005

For the low power and low cost transceivers, direct sequence spread spec01m frequency-shift keying (DSSS-FSK) is proposed. A transmitter of the DSSS-FSK signal can be implemented by a simple direct modulation using the phase locked loop. Since the DSSS-FSK signal has negligible power around the carrier frequency, low cost direct conversion receiver can be used. Optimum coherent and semi-coherent correlation detection methods for the DSSS-FSK signal are proposed and analyzed. Segmented semi-coherent correlation detection method is proposed to improve the bit error rate performance in the large carrier frequency offset.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.1296-1299
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• 2002

We implemented a CD signal processor operated on a CAV 48-speed CD-ROM drive into a VLSI. The CD signal processor is a mixed mode monolithic IC including servo-processor, data recovery, data-processor, and I-bit DAC. For servo signal processing, we included a DSP core, while, for CAV mode playback, we adopted a PLL with a wide recovery range. Data processor (DP) was designed to meet the yellow book specification.［2］So, the DP block consists of EFM demodulator, C1/C2 ECC block, audio processor and a block transferring data to an ATAPI chip. A modified Euclid's algorithm was used as a key equation solver for the ECC block To achieve the high-speed decoding, the RS decoder is operated by a pipelined method. Audio playability is increased by playing a CD-DA disc at the speed of 12X or 16X. For this, subcode sync and data are processed in the same way as main data processing. The overall performance of IC is verified by measuring a transfer rate from the innermost area of disc to the outermost area. At 48-speed, the operating frequency is 210 ㎒, and this chip is fabricated by 0.35 um STD90 cell library of Samsung Electronics.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.11
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• pp.1117-1124
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• 2011

In this paper, we implemented a Ka-band frequency synthesizer for millimeter wave seeker. We improved frequency synthesizer performance of phase noise, resolution and spurious using the DDS driven hybrid method The proposed frequency synthesizer has the bandwidth of 1 GHz, frequency switching time of below 9 ${\mu}s$, suppressed spurious level of below -68.9 dBc. phase noise of -113.58 dBc/Hz at offset 100 kHz and flatness of ${\pm}$0.7 dB.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.11
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• pp.1-9
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• 1996

In the following paper, new architectural algorithm of clock and data recovery circuit is proposed for 622.08 Mbps optical communication receiver. New algorithm makes use of charge pump PLL using voltage controlled ring oscillator and extracts 8-channel 77.76 MHz clock signals, which are delayed by i/8 (i=1,2, ...8), to convert and recover 8-channel parallel data from 662.08 Mbps MRZ serial data. This circuit includes clock genration block to produce clock signals continuously even if input data doesn't exist. And synchronization of data and clock is doen by the method which compares 1/2 bit delayed onput data and decided dta by extracted clock signals. Thus, we can stabilize frequency and phase of clock signal even if input data is distorted or doesn't exist and simplify receiver architecture compared to traditional receiver's. Also it is possible ot realize clock extraction, data decision and conversion simulataneously. Verification of this algorithm is executed by DESIGN CENTER (version 6.1) using test models which are modelized by analog behavior modeling and digital circuit model, modified to process input frequency sufficiently, in SPICE.

• Journal of Power Electronics
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• v.18 no.3
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• pp.853-862
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• 2018

Frequency coupling in the phase domain is a recently reported phenomenon for phase locked loop (PLL) based three-phase grid-inverter systems. This paper investigates the mechanism and stabilization method for the frequency coupling to the stability of grid-inverter systems. Self and accompanying admittance models are employed to represent the frequency coupling characteristics of the inverter, and a small signal equivalent circuit of a grid-inverter system is set up to reveal the mechanism of the frequency coupling to the system stability. The analysis reveals that the equivalent inverter admittance is changed due to the frequency coupling of the inverter, and the system stability is affected. In the end, retuning the bandwidth of the phase locked loop is presented to stabilize the three-phase grid-inverter system. Experimental results are given to verify the analysis and the stabilization scheme.

• Journal of Society of Preventive Korean Medicine
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• v.18 no.3
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• pp.117-128
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• 2014

Objective : It is known that Pueriaria lobata has an anti-osteoporetic effect, anti-cancer effect, anti-pyretic effect, and anti-diabetic effect. The aim of this study was to evaluate anti-obesity effect of Pueriaria lobata extract (PLE), and elucidate the effect of it on gene expression related to lipid metabolism. Method : The experiments were performed with the use of ovariectomized rats as estrogen-deficient obesity model. They were grouped NC (normal control), OC (estrogen-deficient control), PLH (100mg/kg of PLE), PLL (20mg/kg). PLE was orally administered for 6 weeks. Body weights and serum lipid level were estimated, and real-time PCR was performed to investigate the effect of PLE on gene expression in liver. Results : PLE decreased the body weight and serum cholesterol and triglyceride, but increased HDL-cholesterol. And PLE increased leptin, CYP27, CPT1, CYP8B1, ACAT2, LDLR, and SCD1, but reduced $PPAR{\gamma}$, PGC1A, HMG-CoA-R, ACAT1, SCD1, and APoB gene expression in liver tissue of rat with estrogen-deficient obesity. Conclusion : It is concluded that Pueriaria lobata reduced body weight, and its effect was expressed by regulation of gene expression related to lipid metabolism in rats with estrogen-deficient obesity.