• The Transactions of the Korean Institute of Power Electronics
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• v.13 no.3
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• pp.206-212
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• 2008

This paper proposes the PLL(Phase-Locked Loop) algorithm by a new FFT(Fast Fourier Transform) in a grid-connected PV PCS(Photovoltaics Power Conditionning System). The grid-connected inverter that is applied in a new renewable energy field needs the grid phase information for synchronism. Unlike the PLL which is normally used by three phase D-Q conversion, the preposed PLL algorithm using FFT has non-gain tuning and the powerful noise elimination by the characteristics of FFT. Both simulation and experimental result show that proposed algorithm has the good capacity.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.12
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• pp.2370-2378
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• 2009

The enhanced phase angle estimation algorithm is essential to supply the power stably under synchronizing with grid source. In this paper, we are proposed the novel phase angle estimation algorithm and verified the validity of proposed method as simulation with PSIM and experiments. We sort the harmonics element using high-pass filter(HPF) that have the cut-off frequency below basic element and make reverse d-q transformation. So, it can be restored the harmonics element at stationary axis, and we can get the fundamental voltage element of AC grid. Proposed PLL method have a rapid responsibility and a large margin at controller design than conventional method because it have a small phase delay and a sufficient controller gain margin. And, it can reduce the error of voltage rms value and axis transformation according to robust PLL algorithm against the harmonic and phase unbalance.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.6
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• pp.1289-1301
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• 1997

In a SDH network, one of the most important issues is the realization of network synchronization. In this paper, we presented the relationship between parameters and control algorithm of DP-PLL for design in a SDH based time, SSM processing time, PJE counter and reference switching time, and analyzed phase transients for one node and mutiple nodes through our simulation results with a standard specification. We suggested suitable design method of SDH-DP-PLL.

• Proceedings of the KIEE Conference
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• 2008.10c
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• pp.240-242
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• 2008

본 논문에서는 단상 PLL알고리즘 중 하나인 영점검출 방식에서의 순시제어 불능을 극복하기 위해 arcsin을 이용한 알고리즘을 제안하였다. 또한 시뮬레이션을 통해 영점검출과 비교하여 제안된 PLL알고리즘의 순시제어 가능성을 검증하였다.

• Journal of Power Electronics
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• v.16 no.1
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• pp.18-26
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• 2016

This paper proposes a compensation algorithm for reducing a specific ripple component on synchronous reference frame phase locked loop (SRF-PLL) in grid-tied single-phase inverters. In general, SRF-PLL, which is based on all-pass filter to generate virtual voltage, is widely used to estimate the grid phase angle in a single-phase system. In reality, the estimated grid phase angle might be distorted because the phase difference between actual and virtual voltages is not 90 degrees. That is, the phase error is caused by the difference between cut-off frequency of all-pass filter and grid frequency under grid frequency variation. Therefore, the effects on phase angle and output current attributed to the phase error are mathematically analyzed in this paper. In addition, the proportional resonant (PR) controller is adapted to reduce the effects of phase error. The validity of the proposed algorithm is verified through several simulations and experiments.

• Proceedings of the KIPE Conference
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• 2008.06a
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• pp.91-93
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• 2008

In this paper, novel phase angle following algorithm for the single phase grid-connected inverter is proposed. Gird-connected inverter needs phase angle detection for synchronization grid voltage with the inverter output. In case of single phase grid-connected inverter, zero crossing detection and virtual 2-phase PLL using digital all pass filter or digital low pass filter are used conventionally. But these methods have a weakness for harmonics, noises and ripples. The proposed method of PLL achieve DFT(Discrete Fourier Transform) using Goertzel algorithm. It can extract fundamental voltage of grid. As a results, it can obtain phase angle using digital all pass filter without effect of harmonics, noises and ripples. Simulation results are presented to demonstrate the effectiveness of the proposed algorithm.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.28 no.11
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• pp.68-76
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• 2014

This paper presents an offset error compensation algorithm for the accurate phase angle of the grid voltage in single-phase grid-connected inverters. The offset error generated from the grid voltage measurement process cause the fundamental harmonic component with grid frequency in the synchronous reference frame phase lock loop (PLL). As a result, the grid angle is distorted and the power quality in power systems is degraded. In addition, the dq-axis currents in the synchronous reference frame and phase current have the dc component, first and second order ripples compared with the grid frequency under the distorted grid angle. In this paper, the effects of the offset and scaling errors are analyzed based on the synchronous reference frame PLL. Particularly, the offset error can be estimated from the integrator output of the synchronous reference frame PLL and compensated by using proportional-integral controller. Moreover, the RMS (Root Mean Square) function is proposed to detect the offset error component. The effectiveness of the proposed algorithm is verified through simulation and experiment results.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.1B
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• pp.183-192
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• 2000

In this paper, the dual looped CMOS PLL with 3-250MHz input locking range at a single 13.3V is designed. This paper proposed a new PLL architecture with a current pumping algorithm to improve voltage-to-frequencylinearity of VCO(Voltage Controlled Oscillator). The designed VCO operates at a wide frequency range of75.8MHz-lGHz with a high linearity. Also, PFD(Phase frequency Detector) circuit preventing voltage fluctuation of the charge pump with loop filter circuit under the locked condition is designed. The simulation results of the PLL using 0.6 um N-well single poly triple metal CMOS technology illustrate a locking time of 3.5 us, a power dissipation of 92mW at 1GHz operating frequency with 125MHz of input frequency. Measured results show that the phase noise of VCO with V-I converter is -100.3dBc/Hz at a 100kHz offset frequency.

• Journal of the Semiconductor & Display Technology
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• v.14 no.2
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• pp.35-40
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• 2015

This paper presents the sensorless position control of the Permanent Magnet Synchronous Motor (PMSM) using stator flux estimation and Phase Lock Loop (PLL). The field current and the torque current are required in order to perform the vector control of the PMSM. At this time, it is necessary for the torque to know the exact position of the magnetic flux generated by the permanent magnet, because the torque must be applied torque current in the direction orthogonal to the permanent magnet. In general the speed of the PMSM is controlled by using a magnetic position sensor. However, this paper, we estimates the stator flux by using the PLL method without the magnetic position sensor. This method is simple and easy, in addition it has the advantage of a stabile estimation of the rotor. Finally the proposed algorithm was confirmed by experimental results and showed the good performance.

• Proceedings of the KIPE Conference
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• 2014.07a
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• pp.136-137
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• 2014

본 논문에서는 계통 전압이 불평형 및 왜곡되었을 경우에 정확한 위상각을 검출 할 수 있는 DSOGI-QSG(dual second order generalized integrator quadrature signal generation)를 이용한 PLL (phase locked loop) 방법을 제안한다. 제안된 PLL 방법은 기존의 DSOGI-PLL 방법과 비교하기 위해, 전압에 불평형 및 왜곡 사고 발생 시 동기각을 검출하는 시뮬레이션을 하였고, 이를 통해 THD가 개선됨을 입증하였다.