• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.199-202
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• 1998

In this paper, to reduce BER(Bit Error Rate) in satellite ATM Networks, a new scheme for FEC(Forward Error Corection) using multi-stage Viterbi coder is proposed. In terms of structural complexity, proposed multi-stage Viterbi coder is simpler than the traditional single-stage coder based on the same BER performances. and, through simulation, proposed coder shows excellent error correction capabilities, compared with traditional FEC schemes. Also, we propose a selective FEC mechanism that adaptively changes the number of stages to satisfy the QoS(Quality of Service) requirements. This Selective scheme can be easily implemented using the PLCP(Physical Layer Convergence Protocol) frame structure.