• Journal of the Microelectronics and Packaging Society
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• v.17 no.1
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• pp.9-17
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• 2010

In this study, von Mises stress and total strain energy density characteristics of lead pin in PGA (Pin Grid Array) packages have been calculated by using the FEM (Finite Element Method). FEM computation is carried out with various heat treatment conditions of lead pin material under $20^{\circ}$ bending and 50 mm tension condition. Results show that von Mises stress locally concentrated on lead pin corners and interface between lead pin head and solder. von Mises stress and total strain energy density decrease as heat treatment temperature of lead pin increases. Also, round shaped corner of lead pin decreases both von Mises stress and total strain energy density on interface between lead pin head and solder. This means that PGA package reliability can be improved by changing the mechanical property of lead pin through heat treatment. This has been known that solder fatigue life decreases as total strain energy density of solder increases. Therefore, it is recommended that both optimized lead pin shape and optimized material property with high lead pin heat treatment temperature determine better PGA package reliability.

• Journal of the Microelectronics and Packaging Society
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• v.18 no.2
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• pp.29-33
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• 2011

Research about the geometry design of lead pin was carried based on the normal or shear stress of the interface between a lead pin and a PCB in terms of delamination failure. The taguchi method with four design factors of three levels and FEA(Finite element Analysis) are carried under $20^{\circ}$ bending and 50 ${\mu}m$ tension of lead pin. The contact width, d2, between head round and copper pad in PCB is the highest affection factor among design factors by analysis of contribution analysis. Equivalent von Mises stress of 18.7% reduction design is obtained by the parameter design of the taguchi method. Maximum normal stress occurred at contact position between solder outer surface and a Cu pad in PCB. Also, maximum shear stress happened at contact position between solder outer surface and SR layer of PCB. From these calculated results, delamination of the PGA package may be occurred from outer interface of solder to inner interface of solder.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.12 no.7
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• pp.1076-1085
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• 2001

In this paper, the FMM(Fast Multipole Method) combined with GMRES(Generalized Minimal RESidual Method) matrix solver is used to extract the parasitic impedance for complicated 3-D structures in uniform dielectric materials which limit the use of MoM(Method of Moment) due to its large computation time and memory requirement. This algorithm is a fast multipole-accelerated method based on quasistatic analysis and is very efficient for computing impedance between conductors. This paper proved the accuracy and efficiency of the FMM by comparing with MoM in simple examples. Finally the parasitic impedance of FC-PGA(Flip Chip Pin Grid Array) Package pins has been extracted by this algorithm and we have considered the possibility of the EMI/EMC problem caused by the signal interference.