• The Journal of the Korea institute of electronic communication sciences
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• v.9 no.7
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• pp.753-759
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• 2014

This paper introduces the reduction design technique of the resonance phenomenon of the inner PCB based on power integrity from the analysis about the inner power supply line generating RLC resonance. With the technique, the resonant frequency resulted from the structural characteristics of the PCB can be analyzed and allows to predict and the capacitor for resonance phenomenon reduction can be decided as a decoupling capacitor. From the simulation result, it was confirmed that the PCB's resonance phenomenon reduction design technique should have the reduction effect in the inner motherboard of the industrial controller. This research will be contributed to the improvement of the safety of a PDN (Power Delivery Network) structure in the layout design technique of the PCB.

• Journal of Advanced Navigation Technology
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• v.28 no.1
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• pp.129-135
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• 2024

In this paper, an analytical approach for the design and analysis of an aperiodic electromagnetic bandgap (EBG)-based power distribution network (PDN) in high-speed integrated-circuit (IC) packages and printed circuit boards (PCBs) is proposed. Aperiodic EBG is an effective method to solve the noise problem of high-speed IC packages and PCBs. However, its analysis becomes challenging due to increased computation time. To overcome the problem, the proposed analytical method entails deriving impedance parameters for EBG island and the overall PDN, which includes locally placed EBG structures. To validate the proposed method, a test vehicle is fabricated, demonstrating good agreement with the measurements. Significantly, the proposed analytical method reduces computation time by 99.7 %compared to the full-wave simulation method.

• Proceedings of the KIEE Conference
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• 2009.07a
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• pp.1601_1602
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• 2009

본 논문은 SSN(Simultaneous Switching Noise) 이 유전체를 통해 다른 시스템에 유기되는 것을 막기 위한 방법인 EBG(Electromagnetic Band-Gap)에 관한 연구이다. 이에 대한 EBG 구조를 설계하기 위해 PDN(Power Delivery Network)에 주기적인 패턴을 삽입한다. 패키지에 EBG 구조를 적용하기 위해 인쇄 회로기판 범위에서 연구되었던 구조를 변형 및 개조하여 EBG 구조가 내포하고 있는 필터의 차단 주파수의 범위를 넓히며 차단 시작 주파수를 1GHz 아래로 낮추는 소형화 방법을 모색한다. 이 연구에서 실시할 EBG 구조에 대한 간단한 고찰과 인쇄 회로 기판에 적합한 AI-EBG(Alternating impedance Electromagnetic Band-Gap) 구조를 이용한 EBG 의 소형화에 대해 언급하고, 소형화를 위한 3-D EBG 의 설계구조에 대해 설명한다. 그리고 저주파에서 차단특성을 높이기 위한 방법으로 3-D EBG를 사용하고 AI-EBG와 비교하여 차단특성의 변화를 Full-wave 시뮬레이션과 측정으로서 비교한다.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2002.11a
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• pp.324-327
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• 2002

For the characterization of arbitrary shaped printed circuit board, lossy transmission line grid model based on SPICE netlist and analytical plane model based on the segmentation method are proposed in this paper. Two methods are compared with an arbitrary shaped power/ground plane. Furthermore, design considerations for the complete power distribution network structure are discussed to ensure the maximum value of the PDN impedance is low enough across the desired frequency range and to guide decoupling capacitor selection.

• Information and Communications Magazine
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• v.16 no.10
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• pp.125-136
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• 1999

ADSL은 일반 가정이나 SOHO에서 Internet access나 Remote LAN Access와 같은 application을 대상으로 사용하기에 적합하다. 제 2장에서는 CPN에서의 configuration, usage scenario를 알아보고 splitter configuration들과 PDN, SM, TE간의 interface가 어떻게 정의되는가를 살펴보았다. 제 3장에서는 central office의 configuration을 간단히 살펴보고, DSLAM 및 service provider network의 requirement들을 알아보았다. 제 4장에서는 원활한 network adaptation 및 service를 위한 Frame based 및 ATM based ADSL architecture들에 대해 언급하고 가능한 protocol stacks들에 대해 간단히 알아보았다. 또한 home network이나 corporate network에서 필요한 tunneling protocol이나 firewall의 구현가능성도 검토하였다. 현재 이러한 내용들이 ADSL Forum에서 활발히 논의되고 있으나, UADSL을 비롯한 ADSL의 대규모 설치에 따른 field trial 및 service를 통해 장단점이 검증될 것으로 보이며 따라서 앞으로 $1\sim2$년 후에나 좀더 효율적인 ADSL architecture, interface 및 protocol이 표준모델로 정착될 것으로 보인다.

• Journal of the Korean Institute of Telematics and Electronics T
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• v.35T no.1
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• pp.1-6
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• 1998

Our studies diagnose insulation degradation using the method of PD system. In analysis method of degradation, we make use of degradation information that analyzed the phase angle - PD pulse amplitude - degradation time( $\Phi$- PDA - t) pattern and phase angle- PD pulse number - degradation time( $\Phi$- PDN - t) pattern using statistical operators such as skewness(S), kurtosis(K). Secondly using statically operator such as the center of gravity (G), the gradient of the discharge distribution(C), we have analyzed for the prediction of life which we can be obtained the time, occurred of many pulse of small discharge amplitude.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.1 no.2
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• pp.137-143
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• 1997

From now on, the network is being developed into PSTN(public switched telephone network) and PDN(public data network), that is depend on the form of data. The former one pursues sending voice, and the latter one pursues sending data. But it causes big loss of the economy and efficiency. So, ISDN, processing voice and data at same time, gives a big profit to user. To enlarge the ISDN at the narrow area, it is necessary that study to send the mixture form of voice and data in LAN environment. So, this paper proposes the algorithm about the mixture form of voice and data in ethernet and token-ring. that is widely used in these days.

• Proceedings of the KIEE Conference
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• 2007.11a
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• pp.130-131
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• 2007

This study investigates the performances of the signaling techniques including differential signals for the power-distribution network(PDN)s with and without the slit, using a rigorous evaluation method, validated by the FDTD simulation up to 5 GHz.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.42 no.4
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• pp.768-779
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• 2017

Recently, the great number of mobile devices causes excessive data/control traffic problems in the centralized LTE/EPC network and such dramatically increased traffic is emerging as a critical issue. In the Centralized Mobility Management (CMM) based LTE/EPC network, the Packet Data Network Gateway (P-GW) plays the centralized mobility anchor role and it accommodates most of data traffic. To solve this problem, the IETF has proposed the Distributed Mobility Management (DMM) scheme, but it has only focused on the data traffic load balancing and could not solve the control traffic overload problem. In this paper, therefore, we propose a new SDN based hybrid CMM/DMM Mobility Management (C-DMM) architecture based on Packet Network Edge Gateway (P-EGW), and introduce a selection scheme between CMM and DMM according to a device's mobility and the number of PDN connections. In order to prove the efficiency of the proposed architecture and scheme, we compare the data traffic processing load and the control traffic processing load over each scheme by emulating them in the ONOS controller and the Mininet environment.

• Journal of the Microelectronics and Packaging Society
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• v.24 no.4
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• pp.91-95
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• 2017

Package-On-Package (PoP) technology is developing toward smaller form factors with high-speed data transfer capabilities to cope with high DDR4x memory capacity. The common application processor (AP) used for PoP devices in smartphones has the bottom package as logic and the top package as memory, which requires both thermally and electrically enhanced functions. Therefore, it is imperative that PoP designs consider both thermal and power distribution network (PDN) issues. Stacked packages have poorer thermal dissipation than single packages. Since the bottom package usually has higher power consumption than the top package, the bottom package impacts the thermal budget of the top package (memory). This paper investigates the thermal and electrical characteristics of PoP designs, particularly the bottom package. Findings include that via and dense via-cluster volume have an important role to lower thermal resistance to the motherboard, which can be an effective way to manage chip hot spots and reduce the thermal impact on the memory package. A Cu block and dense via-cluster layout with an optimal location are proposed to drain the heat from the chip hot spots to motherboard which will enhance thermal and electrical performance at the design stage. The analytical thermal results can be used for design guidelines in 3D packaging.