• Advances in nano research
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• v.10 no.1
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• pp.91-99
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• 2021

Silicene is an emerging two-dimensional (2D) semiconductor material which has been envisaged to be compatible with conventional silicon technology. This paper presents a theoretical study of uniformly doped silicene with aluminium (AlSi3) Field-Effect Transistor (FET) along with the benchmark of device performance metrics with other 2D materials. The simulations are carried out by employing nearest neighbour tight-binding approach and top-of-the-barrier ballistic nanotransistor model. Further investigations on the effects of the operating temperature and oxide thickness to the device performance metrics of AlSi3 FET are also discussed. The simulation results demonstrate that the proposed AlSi3 FET can achieve on-to-off current ratio up to the order of seven and subthreshold swing of 67.6 mV/dec within the ballistic performance limit at room temperature. The simulation results of AlSi3 FET are benchmarked with FETs based on other competitive 2D materials such as silicene, graphene, phosphorene and molybdenum disulphide.

• Journal of Sensor Science and Technology
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• v.7 no.1
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• pp.73-82
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• 1998

In silicon surface micro-machining, the newly developed GPE(gas-phase etching) process was verified as a very effective method for the release of highly compliant micro-structures. The developed GPE system with anhydrous HF gas and $CH_{3}OH$ vapor was characterized and the selective etching properties of sacrificial layers to release silicon micro-structures were discussed. P-doped polysilicon and SOI(silicon on insulator) substrate were used as a structural layer and TEOS(tetraethyorthdsilicate) oxide, thermal oxide and LTO(low temperature oxide) as a sacrificial layer. Compared with conventional wet-release, we successfully fabricated micro-structures with virtually no process-induced striction and residual product.

• Proceedings of the KIEE Conference
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• 1994.07b
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• pp.1277-1279
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• 1994

In the structure of ZnO/nip-SiC: H/metal substrate amorphous silicon (a-Si:H) solar cells, the effects of inserting a rear textured ZnO in the p-SiC:H/metal interface and a graded bandgap buffer layer in the i/p-SiC:H have been analysed by computer simulation. The incident light was taken to have an intensity of $100mW/cm^2$(AM-1). The thickness of the a-Si:H n, ${\delta}$-doped a-SiC:H p, and buffer layers was assumed to be $200{\AA},\;66{\AA}$, and $80{\AA}$, respectively. The scattering coefficients of the front and back ZnO were taken to be 0.2 and 0.7, respectively. Inserting the rear buffer layer significantly increases the open circuit voltage($V_{oc}$) due to reduction of the i/p interface recombination rate. The use of textured ZnO markedly improves collection efficiency in the long wavelengths( above ${\sim}550nm$ ) by back scattering and light confinement effects, resulting in dramatic enhancement of the short circuit current density($J_{sc}$). By using the rear buffer and textured ZnO, the i-layer thickness of the ceil for obtaining the maximum efficiency becomes thinner(${\sim}2500{\AA}$). From these results, it is concluded that the use of textured ZnO and buffer layer at the backside of the ceil is very effective for enhancing the conversion efficiency and reducing the degradation of a-Si:H pin-type solar cells.

• Proceedings of the KIEE Conference
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• 1995.11a
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• pp.348-351
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• 1995

A modified silicon direct bonding method has been developed alloying an intimate contact between grooved and smooth mirror-polished oxide-free silicon wafers. A regular set of grooves was formed during preparation of heavily doped $p^+$-type grid network by oxide-masking und boron diffusion. Void-free bonded interfaces with filing of the grooves were observed by x-ray diffraction topography, infrared, optical. and scanning electron microscope techniques. The presence of regularly formed grooves in bending plane results in the substantial decrease of dislocation over large areas near the interface. Moreover two strongly misoriented waters could be successfully bonded by new technique. Diodes with bonded a pn-junction yielded a value of the ideality factor n about 1.5 and the uniform distribution of series resistance over the whole area of horded pn-structure. The suitability of the modified technique was confirmed by I - V characteristics of power diodes and reversly switched-on dynistor(RSD) with a working area about $12cm^2$. Both devices demonstrated breakdown voltages close to the calculation values.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.35 no.6
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• pp.616-621
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• 2022

Numerical simulation is a good way to predict the conversion efficiency of solar cells without a direct experimentation and to achieve low cost and high efficiency through optimizing each step of solar cell fabrication. TOPCon industrial solar cells fabricated with n-type silicon wafers on a larger area have achieved a higher efficiency than p-type TOPCon solar cells. Electrical and optical losses of the front surface are the main factors limiting the efficiency of the solar cell. In this work, an optimization of boron-doped emitter surface and front electrodes through numerical simulation using "Griddler" is reported. Through the analysis of the results of simulation, it was confirmed that the emitter sheet resistance of 150 Ω/sq along the front electrodes having a finger width of 20 ㎛, and the number of finger lines ~130 for silicon wafer of M6 size is an optimized technology for the front emitter surface of the n-type TOPCon solar cells that can be developed.

• Current Photovoltaic Research
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• v.8 no.1
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• pp.6-11
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• 2020

The power conversion efficiency (PCE) of a two-terminal tandem solar cell depends upon the tunnel-recombination junction (TRJ) between the top and bottom sub-cells. An optimized TRJ in a tandem cell helps improve its open-circuit voltage (V_oc), short-circuit current density (J_sc), fill factor (FF), and efficiency (PCE). One of the parameters that affect the TRJ is the buffer layer thickness. Therefore, we investigated various TRJs by varying the thickness of the buffer or intermediate layer (TRJ-buffer) in between the highly doped p-type and n-type layers of the TRJ. The TRJ-buffer layer was p-type nc-Si:H, with a doping of 0.06%, an activation energy (E_a) of 43 meV, an optical gap (E_g) of 2.04 eV, and its thickness was varied from 0 nm to 125 nm. The tandem solar cells we investigated were a combination of a heterojunction with intrinsic thin layer (HIT) bottom sub-cell and an a-Si:H (amorphous silicon) top sub-cell. The initial cell efficiency without the TRJ buffer was 7.65% while with an optimized buffer layer, its efficiency improved to 11.74%, i.e., an improvement in efficiency by a factor of 1.53.

• 한국신재생에너지학회:학술대회논문집
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• 2010.11a
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• pp.39.2-39.2
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• 2010

In this work we have investigated electrical and optical properties of interface for ITO/Si with shallow doped emitter. The ITO is prepared by DC magnetron sputter on p-type monocrystalline silicon substrate. As an experimental result, The transmittance at 640nm spectra is obtained an average transmittance over 85% in the visible range of the optical spectrum. The energy bandgap of ITO at oxygen flow from 0% to 4% obtained between 3.57eV and 3.68eV (ITO : 3.75eV). The energy bandgap of ITO is depending on the thickness, sturcture and doping concentration. Because the bandgap and position of absorption edge for degenerated semiconductor oxide are determined by two competing mechanism; i) bandgap narrowing due to electron-electron and electron-impurity effects on the valance and conduction bands (> 3.38eV), ii) bandgap widening by the Burstein-Moss effect, a blocking of the lowest states of the conduction band by excess electrons( < 4.15eV). The resistivity of ITO layer obtained about $6{\times}10^{-4}{\Omega}cm$ at 4% of oxygen flow. In case of decrease resistivity of ITO, the carrier concentration and carrier mobility of ITO film will be increased. The contact resistance of ITO/Si with shallow doped emitter was measured by the transmission line method(TLM). As an experimental result, the contact resistance was obtained $0.0705{\Omega}cm^2$ at 2% oxygen flow. It is formed ohmic-contact of interface ITO/Si substrate. The emitter series resistance of ITO/Si with shallow doped emitter was obtained $0.1821{\Omega}cm^2$. Therefore, As an PC1D simulation result, the fill factor of EWT solar cell obtained above 80%. The details will be presented in conference.

• Current Photovoltaic Research
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• v.2 no.4
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• pp.147-151
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• 2014

A boron doping process using a boron tri-bromide ($BBr_3$) as a boron source was applied to form a $p^+$ emitter layer on an n-type mono-crystalline CZ substrate. Nitrogen ($N_2$) gas as an additive of the diffusion process was varied in order to study the variations in sheet resistance and the uniformity of doped layer. The flow rate of $N_2$ gas flow was changed in the range 3 slm~10 slm. The sheet resistance uniformity however was found to be variable with the variation of the $N_2$ flow rate. The optimal flow rate for $N_2$ gas was found to be 4 slm, resulting in a sheet resistance value of $50{\Omega}/sq$ and having a uniformity of less than 10%. The process temperature was also varied in order to study its influence on the sheet resistance and minority carrier lifetimes. A higher lifetime value of $1727.72{\mu}s$ was achieved for the emitter having $51.74{\Omega}/sq$ sheet resistances. The thickness of the boron rich layer (BRL) was found to increase with the increase in the process temperature and a decrease in the sheet resistance was observed with the increase in the process temperature. Furthermore, a passivated emitter solar cell (PESC) type solar cell structure comprised of a boron doped emitter and phosphorus doped back surface field (BSF) having Ni/Cu contacts yielding 15.32% efficiency is fabricated.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.28A no.10
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• pp.814-820
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• 1991

TaSi$_2$ was formed by rapid thermal annealing(RTA) on BF$_2$ doped single crystalline silicon substrates. The formation and various properties of TaSi$_2$ have been investigated by using 4-point probe, HP414, XRD, and SEM. And the redistribution of boron with RTA has been observed by SIMS. Implanted boron was diffused out into the TaSi$_2$ for RTA temperature but did not significantly affect the formation temperature of TaSi$_2$. Also, the contact resistance for TaSi$_2$/p$^{+}$ region had a low value 22$\Omega$, at contact size of 0.9$\mu$m, and the native oxide formed on Si-substrates by BF$_2$ implantation retarded the formation of TaSi$_2$.

• ETRI Journal
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• v.27 no.4
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• pp.439-445
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• 2005

We introduce a strained-SiGe technology adopting different thicknesses of Si cap layers towards low power and high performance CMOS applications. By simply adopting 3 and 7 nm thick Si-cap layers in n-channel and p-channel MOSFETs, respectively, the transconductances and driving currents of both devices were enhanced by 7 to 37% and 6 to 72%. These improvements seemed responsible for the formation of a lightly doped retrograde high-electron-mobility Si surface channel in nMOSFETs and a compressively strained high-hole-mobility $Si_{0.8}Ge_{0.2}$ buried channel in pMOSFETs. In addition, the nMOSFET exhibited greatly reduced subthreshold swing values (that is, reduced standby power consumption), and the pMOSFET revealed greatly suppressed 1/f noise and gate-leakage levels. Unlike the conventional strained-Si CMOS employing a relatively thick (typically > 2 ${\mu}m$) $Si_xGe_{1-x}$ relaxed buffer layer, the strained-SiGe CMOS with a very thin (20 nm) $Si_{0.8}Ge_{0.2}$ layer in this study showed a negligible self-heating problem. Consequently, the proposed strained-SiGe CMOS design structure should be a good candidate for low power and high performance digital/analog applications.