• Journal of Power Electronics
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• 제9권4호
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• pp.593-603
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• 2009

This paper proposes and describes the design and operational principles of a three-phase three-level nine switch voltage source inverter. The proposed topology consists of three bi-directional switches inserted between the source and the full-bridge power switches of the classical three-phase inverter. As a result, a three-level output voltage waveform and a significant suppression of load harmonics contents are obtained at the inverter output. The harmonics content of the proposed multilevel inverter can be reduced by half compared with two-level inverters. A Fourier analysis of the output waveform is performed and the design is optimized to obtain the minimum total harmonic distortion. The full-bridge power switches of the classical three-phase inverter operate at the line frequency of 50Hz, while the auxiliary circuit switches operate at twice the line frequency. To validate the proposed topology, both simulation and analysis have been performed. In addition, a prototype has been designed, implemented and tested. Selected simulation and experimental results have been provided.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권4호
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• pp.437-444
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• 2015

A high output power voltage controlled oscillator (VCO) in the U-band was implemented using a 65 nm CMOS process. The proposed VCO used a transmission line to increase output voltage swing and overcome the limitations of CMOS technologies. Two varactor banks were used for fine tuning with a 5% frequency tuning range. The proposed VCO showed small variation in output voltage and operated at 51.55-54.18 GHz. The measured phase noises were -51.53 dBc/Hz, -91.84 dBc/Hz, and -101.07 dBc/Hz at offset frequencies of 10 kHz, 1 MHz, and 10 MHz, respectively, with stable output power. The chip area, including the output buffer, is $0.16{\times}0.16mm^2$ and the maximum output power was -0.11 dBm. The power consumption was 33.4 mW with a supply voltage of 1.2-V. The measured $FOM_P$ was -190.8 dBc/Hz.

• Journal of Power Electronics
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• 제11권1호
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• pp.74-81
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• 2011

The cutoff frequency of the output LC filters of PWM inverters limits the control bandwidth of the converter system while it attenuates voltage ripples that are caused by inverter switching activities. For a selected cutoff frequency of an output LC filter, an infinite number of L-C combinations is possible. This paper analyses the characteristics of output LC filters for PWM inverters terms of the L-C combinations. Practical circuit conditions such as no-loads, full resistive-loads, and inductive-load conditions are considered in the analysis. This paper proposes a LC filter design method for PWM inverters considering both the voltage ynamics and he inverter stack size. An experimental PWM inverter system based on the proposed output LC lter design uideline is built and tested.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2006년도 6th International Meeting on Information Display
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• pp.218-221
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• 2006

In this paper, a high-voltage generator with several mA draw output currents using LTPS-TFT technology is proposed. The new generator can be efficiently boosted about +18V output voltages with 5mA draw output currents and power efficiency ${\eta}$ is around 84% under the conditions of +5V power-supply voltage and 250kHz frequency.

• Journal of Power Electronics
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• 제15권5호
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• pp.1207-1216
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• 2015

In order to suppress the low frequency oscillation of the neutral-point voltage for three-level inverters, this paper proposes a new discontinuous pulse width modulation (DPWM) control method. The conventional sinusoidal pulse width modulation (SPWM) control has no effect on balancing the neutral-point voltage. Based on the basic control principle of DPWM, the relationship between the reference space voltage vector and the neutral-point current is analyzed. The proposed method suppresses the low frequency oscillation of the neutral-point voltage by keeping the switches of a certain phase no switching in one carrier cycle. So the operating time of the positive and negative small vectors is equal. Comparing with the conventional SPWM control method, the proposed DPWM control method suppresses the low frequency oscillation of the neutral-point voltage, decreases the output waveform harmonics, and increases both the output waveform quality and the system efficiency. An experiment has been realized by a neutral-point clamped (NPC) three-level inverter prototype based on STM32F407-CPLD. The experimental results verify the correctness of the theoretical analysis and the effectiveness of the proposed DPWM method.

• JSTS:Journal of Semiconductor Technology and Science
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• 제7권4호
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• pp.241-246
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• 2007

This paper presents two novel compensation circuits for leakage current and power supply noise (PSN) in phase locked loop (PLL) using a nanometer CMOS technology. The leakage compensation circuit reduces the leakage current of the charge pump circuit and the PSN compensation circuit decreases the effect of power supply variation on the output frequency of VCO. The PLL design is based on a 32nm predictive CMOS technology and uses a 0.9 V power supply voltage. The simulation results show that the proposed PLL achieves 88% jitter reduction at 440 MHz output frequency compared to the PLL without leakage compensator and its output frequency drift is little to 20% power supply voltage variations. The PLL has an output frequency range of 40 $M{\sim}725$ MHz with a multiplication range of 1-1023, and the RMS and peak-to-peak jitter are 5psec and 42.7 psec, respectively.

• Journal of Power Electronics
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• 제8권4호
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• pp.332-344
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• 2008

High frequency AC (HFAC) power distribution systems delivering power through a high frequency AC link with sinusoidal voltage have the advantages of simple structure and high efficiency. In a multiple module system, where multiple resonant inverters are paralleled to the high frequency AC bus through connection inductors, it is necessary for the output voltage phase angles of the inverters be controlled so that the circulating current among the inverters be minimized. However, the phase angle of the resonant inverters output voltage can not be controlled with conventional phase shift modulation or pulse width modulation. The phase angle is a function of both the phase of the gating signals and the impedance of the resonant tank. In this paper, we proposed a pulse phase modulation (PPM) concept for the resonant inverters, so that the phase angle of the output voltage can be regulated. The PPM can be used to minimize the circulating current between the resonant inverters. The mechanisms of the phase angle control and the PPM were explained. The small signal model of a PPM controlled half-bridge resonant inverter was analyzed. The concept was verified in a half bridge resonant inverter with a series-parallel resonant tank. An HFAC power distribution system with two resonant inverters connected in parallel to a 500kHz, 28V AC bus was presented to demonstrate the applicability of the concept in a high frequency power distribution system.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2004년도 하계학술대회 논문집 Vol.5 No.2
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• pp.722-725
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• 2004

Voltage step-down characteristics in Ring/Dot type piezoelectric transformer were examined as a function of the area of input electrode when the area of output electrode is fixed. The effects of driving frequency and load resistance on the voltage step-down characteristics were also examined. Voltage gain was greatly dependent on the driving frequency and load resistance, and showed a maximum gain at resonance frequency of the step-down transformer. The frequency where the maximum output voltage appears increased about 0.2% as the load resistance increased from 10 to $150\Omega$. As the area of input electrode increased, the voltage gain and the efficiency of the transformer increased. Frequency dependence of efficiency of the step-down transformer revealed a similar tendency with the voltage gain curves. The maximum efficiency remarked 94% when the input voltage and the load resistance were 20 $V_{PP}$ and $120\Omega$, respectively.

• Journal of Power Electronics
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• 제14권5호
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• pp.908-917
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• 2014

For the purpose of designing an intrinsic safety Flyback converter with minimal output voltage ripple based on a specified output current, this paper first classified the energy transmission modes of the system into three sorts, namely, the Complete Inductor Supply Mode-CCM (CISM-CCM), the Incomplete Inductor Supply Mode-CCM (IISM-CCM) and the Incomplete Inductor Supply Mode-DCM (IISM-DCM). Then, the critical secondary self-inductance assorting the three modes are deduced and expressions of the output voltage ripples (OVR) are presented. For a Flyback converter with constant loads and switching frequency, it is shown that the output voltage ripple in the CISM-CCM is the smallest and that it has no relationship with the secondary self-inductance. Otherwise, the OVR of the other two modes are bigger than the previously mentioned one. It is concluded that the critical inductance between the CISM-CCM and the IISM-CCM is the minimal secondary self-inductance to ensure the smallest output voltage ripple. At last, a design method to guarantee the minimum OVR within the scales of the input voltage and load are analyzed, and the minimum secondary self-inductance is proposed to minimize the OVR. Simulations and experiments are given to verify the results.

• Journal of international Conference on Electrical Machines and Systems
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• 제1권4호
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• pp.457-463
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• 2012

Cascaded H-bridge multilevel inverters shows a useful circuit configuration to increase the number of output voltage levels to obtain high quality output voltage. By applying the concept of the power of three to dc voltage sources, it can increase the number of output voltage levels effectively. To realize this concept, two approaches may be considered. One is to use independent dc voltage sources pre-scaled in the power of three, and the other is to use instantaneous dc voltage sources generated from a cascaded transformer, which has the secondary turn-ratios scaled in the power of three in sequence. A common feature in both approaches is to use the concept of the power of three for dc voltage sources, and a point of difference is whether it adopts a low frequency transformer or not, and where the transformer is located. According to the difference, application areas are limited and show different characteristics on THD of output voltages. We compare and analyze both approaches for their circuit configurations, voltage level generating method, THD characteristics of output voltage, efficiency, application areas, limitations, and other characteristics by experiments using 500 [W] prototypes when they generate a 27-level output voltage.