• Title/Summary/Keyword: Output phase control

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Computer-Interfacing Development for Propeller-Anemometer

  • Saad, Nor Hayati;Janin, Zuriati;Piah, Ruhaidawati Mohd Ali
    • 제어로봇시스템학회:학술대회논문집
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    • 2004.08a
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    • pp.515-519
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    • 2004
  • A Propeller-Anemometer is an instrument used specifically, to measure the wind speed. The accurate measurement of the wind speed is vitally important such required by any weather stations. In this research, the measurand of the instrumentation was the rotational speed of the propeller and the instrumentation result or output data was wind velocity. The speed measured was recorded digitally in the computer by using specific software. A specific sensor used to measure a variable by converting information of the variable (rotational speed of the propeller) into a dependent signal such as electrical signal in form of voltage. The development of Propeller-Anemometer involved few sets of instrumentation process and equipment. It included three major parts, mechanical, electronics and computer. The main instrumentation processes were physical and signal interfacing, signal conditioning, logic interfacing, data transmission to computer and processing the data. Generally, this paper presents the overall concept and design of Propeller-Anemometer Instrumentation. However, an emphasis was mainly in designing and building the interfacing system, hardware and software. Basically, for the first phase of the development, this project designed and built the RS232 terminal using Peripheral Interface Controller (PIC), PIC16F873. The hardware can be interfaced to computer or other compatible devices. This routine converted input voltage from the circuit to speed (velocity) and transmitted them afterwards to the target device by using the RS232 transmission protocol. This implementation implied a computer display as visual interface. For the purpose of this paper, RS232 data transmission was carried out using a Microsoft Visual Basic software routine.

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A Slotted Square-Patch Type Balun-BPF (슬롯을 가진 사각 패치형의 발룬-대역 통과 여파기)

  • Oh, Song-Yi;Hwang, Hee-Yong
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.21 no.11
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    • pp.1208-1213
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    • 2010
  • In this paper, a microstrip balun-BPF of slotted-square-patch type is proposed. The conventional balun-BPF has some drawbacks of narrow bandwidth and high insertion loss. In order to improve these weak points, we used a square patch in designing balun-BPF on which two slots intersecting perpendicularly and one corner-edge perturbation are adopted. This structure allows one of the most effective use of the patch space so that the insertion loss can be decreased. Changing the slot lengths is use to control the operating frequency and the bandwidth of the balun-BPF. A fabricated balun-BPF shows wide bandwidth of 300 MHz(12.7 %), small insertion loss of 0.56 dB, phase difference of $184^{\circ}{\pm}15^{\circ}$ and amplitude imbalances of within 1 dB between two output ports at 2.4 GHz band.

A 2.496 Gb/s Reference-less Dual Loop Clock and Data Recovery Circuit for MIPI M-PHY (2.496Gb/s MIPI M-PHY를 위한 기준 클록이 없는 이중 루프 클록 데이터 복원 회로)

  • Kim, Yeong-Woong;Jang, Young-Chan
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.21 no.5
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    • pp.899-905
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    • 2017
  • This paper presents a reference-less dual loop clock and data recovery (CDR) circuit that supports a data rate of 2.496 Gb/s for the mobile industry processor interface (MIPI) M-PHY. An adaptive loop bandwidth scheme is used to implement the fast lock time maintaining a low time jitter. To this scheme, the proposed CDR consists of two loops for a frequency locked loop and a phase locked loop. The proposed 2.496 Gb/s reference-less dual loop CDR is designed using a 65 nm CMOS process with 1.2 V supply voltage. The simulated peak-to-peak jitter of output clock is 9.26 ps for the input data of 2.496 Gb/s pseudo-random binary sequence (PRBS) 15. The active area and power consumption of the implemented CDR are $470{\times}400{\mu}m^2$ and 6.49 mW, respectively.

Instrumentation and system identification of a typical school building in Istanbul

  • Bakir, Pelin Gundes
    • Structural Engineering and Mechanics
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    • v.43 no.2
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    • pp.179-197
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    • 2012
  • This study presents the findings of the structural health monitoring and the real time system identification of one of the first large scale building instrumentations in Turkey for earthquake safety. Within this context, a thorough review of steps in the instrumentation, monitoring is presented and seismic performance evaluation of structures using both nonlinear pushover and nonlinear dynamic time history analysis is carried out. The sensor locations are determined using the optimal sensor placement techniques used in NASA for on orbit modal identification of large space structures. System identification is carried out via the stochastic subspace technique. The results of the study show that under ambient vibrations, stocky buildings can be substantially stiffer than what is predicted by the finite element models due to the presence of a large number of partitioning walls. However, in a severe earthquake, it will not be safe to rely on this resistance due to the fact that once the partitioning walls crack, the bare frame contributes to the lateral stiffness of the building alone. Consequently, the periods obtained from system identification will be closer to those obtained from the FE analysis. A technique to control the validity of the proportional damping assumption is employed that checks the presence of phase difference in displacements of different stories obtained from band pass filtered records and it is confirmed that the "proportional damping assumption" is valid for this structure. Two different techniques are implemented for identifying the influence of the soil structure interaction. The first technique uses the transfer function between the roof and the basement in both directions. The second technique uses a pre-whitening filter on the data obtained from both the basement and the roof. Subsequently the impulse response function is computed from the scaled cross correlation between the input and the output. The overall results showed that the structure will satisfy the life safety performance level in a future earthquake but some soil structure interaction effects should be expected in the North South direction.

On the Development of Authoritative Representations of Torpedo Systems for Engagement Level Simulation (교전수준 어뢰체계 표준모델 개발 방안 연구)

  • Shin, Ji-Hwan
    • Journal of the Korea Society for Simulation
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    • v.16 no.3
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    • pp.19-28
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    • 2007
  • We considered the authoritative representations of torpedo systems that was the engagement level model to develop system specifications and to analyze operational requirements on concept design phase. The Work Breakdown Structure(WBS) of models was defined about authoritative representations of the torpedo systems. The communication of information among each subsystems and input/output parameters were defined. In the heavy weight and light weight torpedo model, presetter, underwater maneuver, war head, sonar, guidance and control, propulsion subsystem modeling were developed for heavy-weight and the light-weight torpedo systems. The authoritative representations of torpedo systems have similar structures with those of the engineering level models and could be verified via engagement level simulations according to the V&V process in the future.

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Three-phase 3-level and 2-level SVPWM Implementation with 100 kHz Switching Frequency using FPGA (FPGA를 이용한 100 kHz 스위칭 주파수의 3상 3-level과 2-level의 SVPWM의 구현)

  • Moon, Kyeong-Rok;Lee, Dong-Myung
    • Journal of IKEEE
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    • v.24 no.1
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    • pp.19-24
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    • 2020
  • This paper presents a 3-level, 2-level SVPWM technique with 100 kHz switching using Verilog HDL, one of the languages of FPGA. In the case of IGBT devices mainly used in inverters, they have a switching frequency around 20kHz. Recent research and development of next-generation power semiconductor devices such as GAN has enabled switching of more than 100kHz, which can miniaturize power converters, and apply various new algorithms due to the injection of harmonics. In the existing system using the IGBT, the control using the DSP is common, but the controller configuration for 100 kHz switching requires the use of FPGA. Therefore, this paper explains the theory and implementation of SVPWM applied to two-level and three-level inverters using FPGAs and verifies the performance through the output waveform. In addition, this paper implements 3-level SVPWM by using only one carrier instead of using two carriers in the conventional method.

Design of Carrier Recovery Circuit for High-Order QAM - Part II : Performance Analysis and Design of the Gear-shift PLL with ATC(Automatic Transfer-mode Controller) and Average-mode-change Circuit (High-Order QAM에 적합한 반송파 동기회로 설계 - II부. 자동모드전환시점 검출기 및 평균모드전환회로를 적용한 Gear-Shift PLL 설계 및 성능평가)

  • Kim, Ki-Yun;Kim, Sin-Jae;Choi, Hyung-Jin
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.38 no.4
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    • pp.18-26
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    • 2001
  • In this paper, we propose an ATC(Automatic Transfer mode Controller) algorithm and an average-mode-change method for use in Gear shift PLL which can automatically change loop gain. The proposed ATC algorithm accurately detects proper timing or the mode change and has a very simpler structure - than the conventional lock detector algorithm often used in QPSK. And the proposed average mode change method can obtain low errors of estimated frequency offset by averaging the loop filter output of frequency component in shift register. These algorithms are also useful in designing ASIC, since these algorithms occupy small circuit area and are adaptable for high speed digital processing. We also present phase tracking performance of proposed Gear-shift PLL, which is composed of polarity decision PD, ATC and average mode change circuit, and analyze the results by examining constellation at each mode.

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Design of a CMOS IF PLL Frequency Synthesizer (CMOS IF PLL 주파수합성기 설계)

  • 김유환;권덕기;문요섭;박종태;유종근
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.40 no.8
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    • pp.598-609
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    • 2003
  • This paper describes a CMOS IF PLL frequency synthesizer. The designed frequency synthesizer can be programmed to operate at various intermediate frequencies using different external LC-tanks. The VCO with automatic amplitude control provides constant output power independent of the Q-factor of the external LC-tank. The designed frequency divider includes an 8/9 or 16/17 dual-modulus prescaler and can be programmed to operate at different frequencies by external serial data for various applications. The designed circuit is fabricated using a 0.35${\mu}{\textrm}{m}$ n-well CMOS process. Measurement results show that the phase noise is 114dBc/Hz@100kHz and the lock time is less than 300$mutextrm{s}$. It consumes 16mW from 3V supply. The die area is 730${\mu}{\textrm}{m}$$\times$950${\mu}{\textrm}{m}$.

A Multi-Section Complex-Coupled DFB Laser with a Very Wide Range of Self-Pulsation Frequency and High Modulation Index (매우 넓은 영역의 Self-Pulsation 주파수와 높은 변조 지수를 가자는 다중 영역 복소 결합 DFB 레이저)

  • Kim, Boo-Gyoun;Kim, Tae-Young;Kim, Sang-Taek;Kim, Sun-Ho;Park, Kyung-Hyun
    • Korean Journal of Optics and Photonics
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    • v.17 no.2
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    • pp.191-197
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    • 2006
  • We analyze the self-pulsation(SP) characteristics due to mode beating of two modes emitted in a multi-section complex-coupled (CC) DFB laser composed of two DFB sections and a phase control section between them. SP frequency due to mode beating of the two modes is determined by the difference of grating periods in the two CC DFB regions. As the difference of grating periods in the two CC DFB regions increases, the SP frequency increases from very low frequency to the THz region. In the case of a mode which is not located in the stop band of the other DFB region, the mode propagates into the other DFB region without a high reflection, so that output powers emitted in a multi-section CC DFB laser have high modulation indexes due to the large interaction between the two modes.

A Study on Low Power Energy Transfer Circuits of the Non Contact Method by means of Solar Generation (태양광 발전에 의한 비접촉 방식 저 전력 에너지 전송회로에 관한 연구)

  • Hwang, Lark-Hoon;Na, Seung-Kwon;Kim, Jong-Rae;Choi, Gi-Ho;Kim, Jin-Seon
    • Journal of Advanced Navigation Technology
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    • v.18 no.1
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    • pp.35-43
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    • 2014
  • In this paper, it is about to non-contact wireless power transmission according to various conditions of self induction principle between the two planar coils at a transmission unit and a receiving unit based on the theory of wireless power transmission. The experiments are occurred in order to power transfer of noncontact method from designed wireless circuits in the primely coil and secondary coil, and the applying to Half Bridge Resonant converter transmission unit and receiving unit. and that were able to prepared circumstance to calculate of the output voltage and power source. The main power of the inductive coupling the resonant converter at the transmission unit is converted electrical energy using the solar cell module and artificial light source (halogen lamp) as a replace light and received 24 V power supply from solar power was used a input power source for the wireless power transmission device. Experimental results, to received of power is used to illuminate the lighting and to charge the battery in receiving circuit.And the wireless power transmission efficiency measured at the output side of the transmission unit is obtained about 70% to 89% compared to input power of receiving unit.In addition, efficiency were tested through ID verification method and comparing the phase difference between the voltage when foreign substances interfere with wireless power transmission.