• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 추계학술대회 논문집 Vol.19
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• pp.127-128
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• 2006

The proposed differential LC cross-coupled VCO is implemented in InGap/GaAs HBT process for an adaptive Global Positioning system(GPS) application. Two filtering capacitors are used at the base of output buffer amplifiers at the both sides of the core m order to improve phase noise characteristics. The VCO produced a phase noise of -133 dBc/Hz at 3MHz offset frequency from the carrier frequency of 1.489GHz and the second harmonic suppression is significantly suppresed up to -49dBc/Hz in simulation result. The three pairs of BC diodes are integrated m the tank circuit to increase the VCO Tunning range.

• 전자공학회논문지D
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• 제35D권5호
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• pp.1-10
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• 1998

A GaAs MMIC composed of VCO (voltage controlled oscillator) and mixer for PCS receiver has been developed using 1.mu.m ion implanted GaAs MESFET process. The VCO consists of a colpitts-type oscillator with a dielectric resonator and the circuit configuration of the mixer is a dual-gate type with an asymmetric combination of LO and RF FETs for the improvement of intermodulation characteristics. The common-source self-biasing is used in all circuits including a buffer amplifier and mixer, achieving a single power supply (3V) operation. The total power dissipation is 78mW. The VCO chip shows a phase noise of-99 dBc/Hz at 100KHz offset. The combined VCO/mixer chip shows a flat conversion gain of 2dB, the frequency-tuning factor of 80MHz/volts in the varacter bias ranging from 0.5V to 0.5V , and output IP3 of dBm at varactor bias of 0V. The fabricated chip size is 2.5mm X 1.4mm.

• 한국통신학회논문지
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• 제26권12C호
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• pp.268-272
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• 2001

본 논문에서는 24.42 GHz 전압제어 Hair-Pin 공진 발진기, 주파수 분주기, 완충 증폭기,-l0 dB 방향성 결합기, 위상 비교기를 이용하여 B-WLL용 PLVCO LO회로를 설계 및 제작하였다. 위상 고정된 발진기는 24.42GHz에서 16.5dBm의 출력을 나타내었으며 위상잡음은 중심주파수 24.42 GHz의 100kHz offset된 지점에서 -76.3 dBc/Hz, 10 kHz offset에서 -72.8 dBc/Hz를 얻었다.

• 한국정보통신설비학회:학술대회논문집
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• 한국정보통신설비학회 2003년도 하계학술대회
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• pp.177-179
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• 2003

본 논문에서는 $0.35{\mu}m$ CMOS 공정을 이용하여 2.5 Gbps로 동작하는 광 송수신기를 설계하였다. 광 송수신기의 구성을 보자면, 전기 신호를 빛 신호로 전환하여 주는 레이저 다이오드(LD) 구동부와 레이저 다이오드에서 나오는 빛 신호를 수신하여 이를 다시 전기 신호로 바꿔주는 포토 다이오드(PD) 구동 부분으로 구성된다. LD 구동부는 LD의 문턱전류 이상을 공급하는 바이어스 부분과 신호레벨의 모듈레이션 전류를 공급하는 부분으로 구성된다. 디자인된 송신기는 바이어스 전류를 10 mA 정도 공급하여주며, 모듈레이션 전류를 15 mA 정도 공급한다. 수신기는 current decision 부분과 output buffer 부분으로 구성되어 PD로부터 나오는 전류를 다시 디지털 레벨의 전압신호로 바꾸어 주며 디자인된 수신기는 넓은 동작 영역을 가진다.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2003년도 International Meeting on Information Display
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• pp.72-75
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• 2003

For the analog output buffer in the data driver for large size and high resolution TFT-LCDs, we proposed operational amplifier (op-amp) which contains newly developed transconductance-boosted input stage which enables the low-power consumption and the high slew-rate. The slew-rate and the quiescent current of the proposed op-amp are $6.1V/{\mu}sec$ and $8{\mu}A$, respectively.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.927-930
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• 2003

In this paper, a design of processor IP for TCP/IP protocol stack is described. The processor consists of input and output buffer memory with dual bank structure, 32-bit RISC microprocessor core, DMA unit with on-the-fly checksum capability. To handle the various modes of TCP/IP protocol, hardware and software co-design approach is used rather than the conventional state machine based design. To eliminate delay time due to the data transfer and checksum operation, DAM module which can execute the checksum operation on-the-fly along with data transfer operation is adopted. By programming the on-chip code ROM of RISC processor differently. the designed stack processor can support the packet format conversion operations required in the various TCP/IP protocols.

• ETRI Journal
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• 제25권4호
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• pp.270-273
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• 2003

This paper presents a simple process to integrate thin-film inductors with a bottom NiFe magnetic core. NiFe thin films with a thickness of 2 to 3${\mu}m$ were deposited by sputtering. A polyimide buffer layer and shadow mask were used to relax the stress of the NiFe films. The fabricated double spiral thin-film inductor showed an inductance of 0.49${\mu}H$ and a Q factor of 4.8 at 8 MHz. The DC-DC converter with the monolithically integrated thin-film inductor showed comparable performances to those with sandwiched magnetic layers. We simplified the integration process by eliminating the planarization process for the top magnetic core. The efficiency of the DC-DC converter with the monolithic thin-film inductor was 72% when the input voltage and output voltage were 3.5 V and 6 V, respectively, at an operating frequency of 8 MHz.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
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• pp.369-372
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• 2001

This paper presents the design of high-speed virtual output queue(VOQ) management scheme for high performance cell/packet switch, which has a serial cross bar structure. The proposed VOQ management scheme has been designed for wire-speed routing with a pipelined buffer management. It provides the tolerance of requests and grants data transmission latency between the VOQ manager and central arbiter using a new request control method that is based on a high-speed shifter. The designed VOQ manager has been implemented in a field programmable gate array chip with a 77MHz operating frequency, a 900-pin fine ball grid array package, and 16$\times$16 switch size.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 하계종합학술대회 논문집
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• pp.122-125
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• 1999

In this paper, we propose a new architecture of the Banyan switch for a high speed networking and the high speed parallel computer. The proposed switching network with a remodeled architecture is a newly modified Banyan network with eight input and output pots, respectively. We have analysed the maximum throughput of the revised switch. Our analyses has shown that under the uniform random traffic load, the FIFO discipline is limited to 70％. Therefore the result of the analyses shows that the results of the networking simulation with the new switch are feasible and if we adopt such as new architecture of the revised model of the Banyan switch, the hardware complexity can be reduced. The FIFO discipline has increased about 11% when we compare the switching system with the input buffer system. We have designed and verified the new switching system in VHDL.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 추계종합학술대회 논문집
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• pp.689-692
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• 1999

This paper describes a 10-bit 75-MHz CMOS current-mode DAC designed for 0.8${\mu}{\textrm}{m}$ double-poly double-metal CMOS technology. This D/A converter is implemented using a current cell matrix that can drive a resistive load without output buffer. In the DAC. a current source is proposed to reduce the linearity error caused by the threshold-voltage variations over a wafer and the glitch energy caused by the time lagging, The integral and differential linearity error are founded to be within $\pm$0.35 LSB and $\pm$0.31 LSB respectively. The maximum conversion rate is about 80 MS/s. The total power dissipation is 160 ㎽ at 75 MS/s conversion rate.