• 전력전자학회논문지
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• 제27권4호
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• pp.348-355
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• 2022

A bipolar DC distribution system suffers from an imbalance in voltages when asymmetric loads are connected at the outputs. Dedicated voltage balancers are required to address the imbalance in bipolar voltage levels. However, additional components eventually increase the cost and decrease the efficiency and power density of the system. Therefore, to deal with the imbalance in output voltages without adding any extra components, this study presents a coupled inductor-based voltage balancing technique with a dual-output CLL resonant converter. The proposed coupled inductor does not require extra magnetic components to balance the output voltages because it is the result of resonant inductors of the CLL tank circuit. It can also avoid complex control schemes applied to voltage balancing. Moreover, with the proposed coupled inductor, the CLL converter acquires good features including zero voltage and zero current switching. Detailed analysis of the proposed coupled inductor is presented with different load conditions. A 3.6-kW hardware prototype was built and tested to validate the performance of the proposed coupled inductor-based voltage balancing technique.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2008년도 하계학술대회 논문집
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• pp.502-504
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• 2008

A new output inductor less phase shift full bridge converter with current reduction technique for server power application is proposed in this paper. The proposed converter can reduce the current stress by using the auxiliary circuit. Since the auxiliary circuit causes the additional resonance between the leakage inductor and auxiliary capacitor before the powering period, the proposed converter has lower current stress even no output filter inductor. Small size and circulating energy can be also the merits of the proposed converter. The operational principles and analysis are presented. Experimental results demonstrate that the current stress can be reduced effectively by using the auxiliary circuit without large output filter inductor.

• IEIE Transactions on Smart Processing and Computing
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• 제4권1호
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• pp.44-50
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• 2015

This paper presents a high speed synchronous single inductor dual output boost converter using Type-III compensation for power management in smart devices. Maintaining multiple outputs from a single inductor is becoming very important because of inductor the sizes. The uses of high switching frequency, inductor and capacitor sizes are reduced. Owing to synchronous rectification this kind of converter is suitable for SoC. The phase is controlled in time sharing manner for each output. The controller used here is Type-III, which ensures quick settling time and high stability. The outputs are stable within $58{\mu}s$. The simulation results show that the proposed scheme achieves a better overall performance. The input voltage is 1.8V, switching frequency is 5MHz, and the inductor used is 600nH. The output voltages and powers are 2.6V& 3.3V and 147mW &, 230mW respectively.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권3호
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• pp.300-312
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• 2014

A single-inductor multiple-output (SIMO) DC-DC converter providing buck and boost outputs with a new switching sequence is presented. In the proposed switching sequence, which does not require any additional blocks, input energy is delivered to outputs continuously by flowing current through the inductor, which leads to high conversion efficiency regardless of the balance between the buck and boost output loads. Furthermore, instead of multiple output loop compensation, only the freewheeling current feedback loop is compensated, which minimizes the number of off-chip components and nullifies the need for the equivalent series resistance (ESR) of the output capacitor for loop compensation. Therefore, power conversion efficiency and output voltage ripples can be improved and minimized, respectively. Implemented in a 0.35-${\mu}m$ CMOS, the proposed SIMO DC-DC converter achieves high conversion efficiency regardless of the load balance between the two outputs with maximum efficiency reaching up to 82% under heavy loads.

• Journal of Power Electronics
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• 제4권2호
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• pp.87-95
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• 2004

A new fast-response high-current clamp DC-DC converter circuit design is presented that will meet the requirements and features of the new generation of microprocessors and digital systems. The clamp in the proposed converter amplifies the current in case of severe load changes and is able to produce high slew rate of output current and capability to keep constant the output voltage. This proposed high-current clamp technique is theoretically loss less, low cost and easy to implement with simple control scheme. This is modified from a basic buck topology by replacing the output inductor with two magnetically coupled inductors. Inductors are difference in inductance, one has large inductance and other has small inductance. The inductor with small inductance will take over the output inductor during fast load transient. It speedup the output current slew rate and reduce the output voltage drop in the case of heavy burden load changes.

• Journal of Power Electronics
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• 제5권1호
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• pp.67-75
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• 2005

A high efficiency ZVS PWM asymmetrical half bridge converter for a plasma display panel (PDP) sustaining power modules is proposed in this paper. To achieve the ZVS of power switches for the wide load range, a small additional inductor L/sub 1kg/, which also acts as an output filter inductor, is serially inserted into the transformer's primary side. At that point, to solve the problem of ringing in the secondary rectifier caused by L/sub 1kg/, the proposed circuit employs a structure without the output filter inductor, which helps the voltages across rectifier diodes to be clamped at the output voltage. Therefore, no dissipative RC (resistor capacitor) snubber for rectifier diodes is needed and a high efficiency as well as low noise output voltage can be realized. In addition, since it has no large output inductor filter, the asymmetrical half bridge converter features a simpler structure, lower cost, less mass, and lighter weight. In addition, since all energy stored in L/sub 1kg/ is transferred to the output side, the circulating energy problem can be effectively solved. The operational principle, theoretical analysis, and design considerations are presented. To confirm the operation, validity, and features of the proposed circuit, experimental results from a 425W, 385Vdc/170Vdc prototype are presented.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2004년도 전력전자학술대회 논문집(2)
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• pp.537-541
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• 2004

A high efficiency ZVS PWM asymmetrical half bridge converter for a plasma display panel (PDP) sustaining power module is proposed in this paper. To achieve the ZVS of power switches for the wide fond range, n small additional inductor $L_{lkg}$, which also acts as an output filter inductor, is serially inserted to the transformer primary side. Then, to solve the problem related to ringing in the secondary rectifier caused by $L_{lkg}$, the proposed circuit employs a structure without the output filter inductor, which helps the voltages across rectifier diodes to be clamped at the output voltage. Therefore, no dissipative RC (resistor capacitor) snubber for rectifier diodes is needed and n high efficiency as well as low noise output voltage can be realized. In addition, since it has no large output inductor filter, it features a simpler structure, lower cost, less mass, and lighter weight. Moreover, since all energy stored in $L_{lkg}$ is transferred to the output side, the circulating energy problem can be effectively solved. The operational principle, theoretical analysis, and design considerations are presented. To confirm the operation, validity, and features of the proposed circuit, experimental results from a 425W, 385Vdc/170Vdc prototype are presented.

• 전력전자학회논문지
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• 제20권1호
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• pp.81-90
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• 2015

This paper investigates the droop control-based real and reactive power load sharing with a virtual inductor when the line impedance between inverter and Point of Common Coupling (PCC) is partly and unequally resistive in high-capacity systems. In this paper, the virtual inductor method is applied to parallel inverter systems with resistive and inductive line impedance. Reactive power sharing error has been improved by applying droop control after considering each line impedance voltage drop. However, in high capacity parallel systems with large output current, the reference output voltage, which is the output of droop controller, becomes lower than the rated value because of the high voltage drop from virtual inductance. Hence, line impedance voltage drop has been added to the droop equation so that parallel inverters operate within the range of rated output voltage. Additionally, the virtual inductor value has been selected via small signal modeling to analyze stability in transient conditions. Finally, the proposed droop method has been verified by MATLAB and PSIM simulation.

• 조명전기설비학회논문지
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• 제26권6호
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• pp.16-28
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• 2012

This paper proposes a quasi Z-source converter(QZSC) with a diode-capacitor output filter to improve the output DC voltage boost ability. The proposed converter has the same quasi Z-source network topology compared with the conventional converter. But the proposed method is adopted a diode-capacitor filter as its output filter, since the conventional method is used an inductor-capacitor as its output filter. Under the condition of the same input-output DC voltage, the proposed method has more lower shoot-through duty ratio than the conventional method. Also, because the proposed converter has same voltage boost factor under lower shoot-through duty ratio compared with the conventional converter, the proposed converter can be operated with the lower capacitor voltage of Z-source network and the lower input current. To confirm the validity of the proposed method, PSIM simulation and a DSP based experiment were performed to acquire the output DC voltage 120[V] under the input DC voltage 80[V]. And the capacitor voltage and inductor current in Z-source network, the output voltage of each converter were compared and discussed.

• 전기전자학회논문지
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• 제18권2호
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• pp.220-227
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• 2014

이 논문은 Dead-time을 갖는 톱니파 발생기를 이용하여 공통모드와 차동모드 피드백 루프를 구현한 Single-Inductor Dual-Output DC-DC Converter 설계에 관한 내용을 제시하고 있다. 제어회로에는 공통모드와 차동모드 피드백 루프를 Dead-time을 갖는 톱니파 발생기를 이용하여 동시에 사용하였다. 차동모드 피드백 루프에서 duty를 생성하기 위해서 전류 분배기 회로를 사용하여 공통모드 피드백에 의한 duty에 따라 dead-time이 유동적으로 변하는 톱니파형을 만드는 회로인 Dead-time을 갖는 톱니파 발생기를 추가하여 차동모드 피드백 회로를 구성하였다. 0.35um 공정을 사용하여 설계한 SIDO DC-DC Converter는 2.5V 입력으로부터 2.8V와 4.2V의 전압을 출력하며 최대 전력변환 효율은 95%이다. 출력간의 Cross regulation은 출력전류가 2배씩 증가할 경우 Boost1과 Boost2의 출력전압은 각각 3.57%, 4% 수준을 보이고 있다.