• Journal of Korea Multimedia Society
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• v.21 no.2
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• pp.232-241
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• 2018

Operational Transformation (OT) algorithms for real-time collaborative editing systems are becoming increasingly important due to the increased demand for collaborative data processing. The operational transformation algorithm is a technique for real-time concurrency control and consistency maintenance with non-locking technique, and many studies have been conducted to overcome three issues of convergence, causality-prevention, and intention-prevention. However, previous work has the disadvantage of wasting memory by storing all operations that occurred during an edit operation in the history buffer to solve this problem. Therefore, we propose a memory-saving real-time collaborative editing system that maintains a constant memory space and concurrency control through a method of applying the valid-time to each user-generated operation in order to reduce memory waste. This system prevents long-term memory occupation of client-generated operations, thus it reduces the space and time complexity even with low-rate of collaboration work, so that the performance degradation avoids.

• Phonetics and Speech Sciences
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• v.3 no.4
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• pp.95-102
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• 2011

The purpose of this study was to identify the characteristics of the phonological discrimination ability and phonological working memory of 10 typically developing children aged 4, and 10 other children with Specific Language Impairments whose language age is similar. In orders to compare their phonological discrimination ability among phonological awareness, discrimination tasks were conducted at the syllable and phoneme levels. Also, in order to compare their phonological working memory, the subjects repeated nonsense syllables. The research results may be summarized as follows: First, the children with Specific Language Impairments demonstrated a lower performance than the typically developing children in phonological discrimination ability at both syllable and phoneme levels, and the difference between the groups was statistically significant. Second, the children with Specific Language Impairments exhibited a lower phonological working memory performance in all syllables compared with normal children. Although there was no significant difference in 2 and 3 syllables, a significant difference appeared as the length of the syllables became longer from 4 to 6 syllables. It is deemed necessary to conduct research into qualitative and quantitative differences through an formal assessment of the phonological awareness and phonological working memory of children with Specific Language Impairments.

• Journal of the Korean Society for Heat Treatment
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• v.27 no.2
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• pp.59-64
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• 2014

Cu-Al-Mn shape memory alloys of a variety of composition were characterized in terms of shape memory properties and cold workability. Cold workability tested by cold rolling indicated that the alloys solution treated in the ${\alpha}+{\beta}$ region have a higher ductility than those solution treated in the ${\beta}$ region. Also it is known that cold workability increased with the decrease in Al content in the ${\beta}$ region. This seems to be resulted from the fact that Mn addition causes to expand ${\beta}$ region toward lower Al content and lower order-disorder transition temperature, consequently, ${\beta}$ of excellent workability being frozen even at room temperature. Experimental results regarding shape memory showed that the properties were better with a higher Al contents at a given Mn content, which is closely related with martensitic transformation. It is also shown that super elasticity limit was enhanced with decrease in the yield strength of alloys because a lower yield strength seems to initiates slip at the lower applied stress.

• KIPS Transactions on Computer and Communication Systems
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• v.5 no.1
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• pp.1-6
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• 2016

This paper focuses on algorithm innovation of NAND Flash Memory for enhancing cell lifetime. During flash memory read/write/erase, the voltage of a specific cell should be a valid voltage level. If not, we cannot read the data correctly. This type of interference/disturbance tends to be serious when program and erase operation will go on. This is because FN tunneling results in tunnel oxide damage due to increased trap site on repetitive high biased state. In order to resolve this problem, we make the cell degradation by reducing the amount of stress in terms of erase cell, resulting in minimizing the cell disturbance on erase verify.

• Journal of Institute of Control, Robotics and Systems
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• v.13 no.5
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• pp.393-398
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• 2007

In this paper, we propose the development of Artificial Hippocampus Algorithm(AHA) which remodels a principle of brain of hippocampus. Hippocampus takes charge auto-associative memory and controlling functions of long-term or short-term memory strengthening. We organize auto-associative memory based 4 steps system (EC, DG CA3, and CA1) and improve speed of teaming by addition of modulator to long-term memory teaming. In hippocampus system, according to the 3 steps order, information applies statistical deviation on Dentate Gyrus region and is labeled to responsive pattern by adjustment of a good impression. In CA3 region, pattern is reorganized by auto-associative memory. In CA1 region, convergence of connection weight which is used long-term memory is learned fast a by neural network which is applied modulator. To measure performance of Artificial Hippocampus Algorithm, PCA(Principal Component Analysis) and LDA(Linear Discriminants Analysis) are applied to face images which are classified by pose, expression and picture quality. Next, we calculate feature vectors and learn by AHA. Finally, we confirm cognitive rate. The results of experiments, we can compare a proposed method of other methods, and we can confirm that the proposed method is superior to the existing method.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.32-35
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• 2002

The work focuses on the development of a Cu lead-frame with a single-sided adhesive tape for cost reduction and reliability improvement of LOC (lead on chip) package products, which are widely used for the plastic-encapsulation of memory chips. Most of memory chips are assembled by the LOC packaging process where the top surface of the chip is directly attached to the area of the lead-frame with a double-sided adhesive tape. However, since the lower adhesive layer of the double-sided adhesive tape reveals the disparity in the coefficient of thermal expansion from the silicon chip by more than 20 times, it often causes thermal displacement-induced damage of the IC pattern on the active chip surface during the reliability test. So, in order to solve these problems, in the resent work, the double-sided adhesive tape is replaced by a single-sided adhesive tape. The single-sided adhesive tape does net include the lower adhesive layer but instead, uses adhesive materials, which are filled in clear holes of the base film, just for the attachment of the lead-frame to the top surface of the memory chip. Since thermal expansion of the adhesive materials can be accommodated by the base film, memory product packaged using the lead-flame with the single-sided adhesive tape is shown to have much improved reliability. Author allied this invention to the Korea Patent Office for a patent (4-2000-00097-9).

• The Journal of the Korea institute of electronic communication sciences
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• v.10 no.2
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• pp.275-282
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• 2015

Since a NAND-flash memory is able to keep data during electricity-off and has small cost to store data per bytes, it is widely used on hand-held devices. It is necessary to use an index in order to process mass data effectively on the flash memory. However, since the flash memory requires high cost for a write operation and does not support an overwrite operation, it is possible to reduce the performance of the index when the disk based index is exploited. In this paper, we implement the fixed grid file index and evaluate the performance of the index on various conditions. To do this, we measure the average processing time by the ratio of query operations and update operations. We also the compare the processing times of the flash memory with those of the magnetic disk.

• Journal of the Korea Society of Computer and Information
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• v.24 no.8
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• pp.9-17
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• 2019

In this paper, we propose a block mapping technique applicable to NAND flash memory. In order to use the NAND flash memory with the operating system and the file system developed on the basis of the hard disk which is mainly used in the general PC field, it is necessary to use the system software known as the FTL (Flash Translation Layer). FTL overcomes the disadvantage of not being able to overwrite data by using the address mapping table and solves the additional features caused by the physical structure of NAND flash memory. In this paper, we propose a new mapping method based on the block mapping method for efficient use of the NAND flash memory. In the case of the proposed technique, the data modification operation is processed by using a blank page in the existing block without using an additional block for the data modification operation, thereby minimizing the block unit deletion operation in the merging operation. Also, the frequency of occurrence of the sequential write request and random write request Accordingly, by optimally adjusting the ratio of pages for recording data in a block and pages for recording data requested for modification, it is possible to optimize sequential writing and random writing by maximizing the utilization of pages in a block.

• Korean Journal of Materials Research
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• v.19 no.9
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• pp.462-467
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• 2009

The Charge Trap Flash (CTF) memory device is a replacement candidate for the NAND Flash device. In this study, Pt/$Al_2O_3/La_2O_3/SiO_2$/Si multilayer structures with lanthanum oxide charge trap layers were fabricated for nonvolatile memory device applications. Aluminum oxide films were used as blocking oxides for low power consumption in program/erase operations and reduced charge transports through blocking oxide layers. The thicknesses of $SiO_2$ were from 30 $\AA$ to 50 $\AA$. From the C-V measurement, the largest memory window of 1.3V was obtained in the 40 $\AA$ tunnel oxide specimen, and the 50 $\AA$ tunnel oxide specimen showed the smallest memory window. In the cycling test for reliability, the 30 $\AA$ tunnel oxide sample showed an abrupt memory window reduction due to a high electric field of 9$\sim$10MV/cm through the tunnel oxide while the other samples showed less than a 10% loss of memory window for $10^4$ cycles of program/erase operation. The I-V measurement data of the capacitor structures indicated leakage current values in the order of $10^{-4}A/cm^2$ at 1V. These values are small enough to be used in nonvolatile memory devices, and the sample with tunnel oxide formed at $850^{\circ}C$ showed superior memory characteristics compared to the sample with $750^{\circ}C$ tunnel oxide due to higher concentration of trap sites at the interface region originating from the rough interface.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.7
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• pp.30-36
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• 2011

Three-dimensional (3D) memories using through-silicon vias (TSVs) as vertical bus across memory layers are implemented by many semiconductor companies. 3D memories are composed of known-good-dies (KGDs). If additional faults are arisen during bonding, they should be repaired. In order to enhance the yield of 3D memories with inter-die redundancies, a die-matching method is needed to effectively stack memory dies in a 3D memory. In this paper, a new die-matching method is proposed for 3D memory yield enhancement with inter-die redundancies considering additional faults arisen during bonding. Three boundary-limited conditions are used in the proposed die-matching method; they set bounds to the search spaces for selecting memory dies to manufacture a 3D memory. Simulation results show that the proposed die-matching method can greatly enhance the 3D memory yield.