• Title/Summary/Keyword: Order memory

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The Efficient Memory BISR Architecture using Sign Bits (Sign Bit을 사용한 고효율의 메모리 자체 수리 회로 구조)

  • Kang, Il-Kwon;Kang, Sung-Ho
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.44 no.12
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    • pp.85-92
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    • 2007
  • With the development of the memory design and process technology, the production of high-density memory has become a large scale industry. Since these memories require complicated designs and accurate manufacturing processes, It is possible to exist more defects. Therefore, in order to analyze the defects, repair them and fix the problems in the manufacturing process, memory repair using BISR(Built-In Self-Repair) circuit is recently focused. This paper presents an efficient memory BISR architecture that uses spare memories effectively. The proposed BISR architecture utilizes the additional storage space named 'sign bit' for the repair of memories. This shows the better performance compared with the previous works.

Effects of Source Recall Conditions on the Relationships among Source Monitoring, Inhibitory Control, and Working Memory (출처 회상 조건이 출처 감찰과 억제적 통제, 작업 기억 간의 관계에 미치는 영향)

  • Lee, Seungjin
    • Korean Journal of Child Studies
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    • v.38 no.2
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    • pp.107-117
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    • 2017
  • Objective: Whereas some studies have suggested that source monitoring is significantly associated with working memory and inhibitory control, both of which are components of executive functioning, other studies have argued otherwise. The author of this study determined that such contradictory findings are a result of heterogeneity in the assessment methods for source monitoring. Therefore, this study aimed at exploring whether the relationships among source monitoring, working memory, and inhibitory control may be altered depending on the differences of source recall conditions. Methods: Eighty children aged 5-8 years saw interesting activities via two different sources. Their source memories on the activity were assessed subsequently. The children were assigned to either the "continuous" source recall group or "non-continuous" source recall group. Both groups participated in working memory and inhibitory control tasks. Results: The results showed that working memory was significantly related to source monitoring regardless of the condition of source recall (continuous vs non-continuous). On the other hand, inhibitory control was significantly associated with source monitoring only in the non-continuous source recall group. Conclusion: Based on these results, the author discussed the need to consider the conditions of source recall during investigative interviews with children in order to induce accurate source monitoring, as part of our effort to interpret the inconsistency of results in the literature and to draw potential applications.

A Real-time Dynamic Storage Allocation Algorithm Supporting Various Allocation Policies (다양한 할당 정책을 지원하는 실시간 동적 메모리 할당 알고리즘)

  • 정성무
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.25 no.10B
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    • pp.1648-1664
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    • 2000
  • This paper proposes a real-time dynamic storage allocation algorithm QSHF(quick-segregated-half-fit) that provides various memory allocation policies. that manages a free block list per each word size for memory requests of small size good(segregated)-fit policy that manages a free list per proper range size for medium size requests and half-fit policy that manages a free list per proper range size for medium size requests and half-fit policy that manages a free list per each power of 2 size for large size requests. The proposed algorithm has the time complexit O(1) and makes us able to easily estimate the worst case execution time(WCET). This paper also suggests two algorithm that finds the proper free list for the requested memory size in predictable time and if the found list is empty then finds next available non-empty free list in fixed time. In order to confirm efficiency of the proposed algorithm we simulated the memory utilization of each memory allocation policy. The simulation result showed that each policy guarantees the constant WCET regardless of memory size but they have trade-off between memory utilization and list management overhead.

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Effect of Cold Rolling on Fatigue Crack Propagation of TiNi/A16061 Shape Memory Composite (TiNi/A16061 형상기억복합재료의 피로균열진전에 대한 냉간압연효과)

  • Lee Jin-Kyung;Park Young-Chul;Lee Kyu-Chang;Lee Sang-Pill;Cho Youn-Ho;Lee Joon-Hyun
    • Transactions of the Korean Society of Mechanical Engineers A
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    • v.29 no.10 s.241
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    • pp.1315-1320
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    • 2005
  • TiNi alloy fiber was used to recover the original shape of materials using its shape memory effect. The shape memory alloy plays an important role within the metal matrix composite. The shape memory alloy can control the crack propagation in metal matrix composite, and improve the tensile strength of the composite. In this study, TiNi/A16061 shape memory alloy(SMA) composite was fabricated by hot press method, and pressed by a roller for its strength improvement. The four kinds of specimens were fabricated with $0\%,\;3.2\%,\;5.2\%\;and\;7\%$ and volume fraction of TiNi alloy fiber, respectively. A fatigue test has performed to evaluate the crack initiation and propagation for the TiNi/A16061 SMA composite fabricated by かis method. In order to study the shape memory effect of the TiNi alloy fiber, the test has also done under both conditions of the room temperature and high temperature. The relationship between the crack growth rate and the stress intensity factor was clarified for the composite, and the cold rolling effect was also studied.

A Novel Memory Hierarchy for Flash Memory Based Storage Systems

  • Yim, Keno-Soo
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.5 no.4
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    • pp.262-269
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    • 2005
  • Semiconductor scientists and engineers ideally desire the faster but the cheaper non-volatile memory devices. In practice, no single device satisfies this desire because a faster device is expensive and a cheaper is slow. Therefore, in this paper, we use heterogeneous non-volatile memories and construct an efficient hierarchy for them. First, a small RAM device (e.g., MRAM, FRAM, and PRAM) is used as a write buffer of flash memory devices. Since the buffer is faster and does not have an erase operation, write can be done quickly in the buffer, making the write latency short. Also, if a write is requested to a data stored in the buffer, the write is directly processed in the buffer, reducing one write operation to flash storages. Second, we use many types of flash memories (e.g., SLC and MLC flash memories) in order to reduce the overall storage cost. Specifically, write requests are classified into two types, hot and cold, where hot data is vulnerable to be modified in the near future. Only hot data is stored in the faster SLC flash, while the cold is kept in slower MLC flash or NOR flash. The evaluation results show that the proposed hierarchy is effective at improving the access time of flash memory storages in a cost-effective manner thanks to the locality in memory accesses.

An Alternative State Estimation Filtering Algorithm for Temporarily Uncertain Continuous Time System

  • Kim, Pyung Soo
    • Journal of Information Processing Systems
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    • v.16 no.3
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    • pp.588-598
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    • 2020
  • An alternative state estimation filtering algorithm is designed for continuous time systems with noises as well as control input. Two kinds of estimation filters, which have different measurement memory structures, are operated selectively in order to use both filters effectively as needed. Firstly, the estimation filter with infinite memory structure is operated for a certain continuous time system. Secondly, the estimation filter with finite memory structure is operated for temporarily uncertain continuous time system. That is, depending on the presence of uncertainty, one of infinite memory structure and finite memory structure filtered estimates is operated selectively to obtain the valid estimate. A couple of test variables and declaration rule are developed to detect uncertainty presence or uncertainty absence, to operate the suitable one from two kinds of filtered estimates, and to obtain ultimately the valid filtered estimate. Through computer simulations for a continuous time aircraft engine system with different measurement memory lengths and temporary model uncertainties, the proposed state estimation filtering algorithm can work well in temporarily uncertain as well as certain continuous time systems. Moreover, the proposed state estimation filtering algorithm shows remarkable superiority to the infinite memory structure filtering when temporary uncertainties occur in succession.

The Effects of Working Memory Load on Word Frequency (작업기억 부하가 단어빈도에 미치는 효과)

  • Lee, Chang-Hoan;Oh, Ji-Hyang;Pyun, Sung-Bom;Lim, Heui-Seok
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.10 no.3
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    • pp.567-571
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    • 2009
  • This study was conducted in order to investigate the role of working memory in word recognition. As a preliminary step in tackling this topic, word frequency and working memory load were manipulated in a naming task. The results showed that word frequency is significantly involved with the working memory load. The effects of working memory load were greater in low-frequency word processing than in high-frequency word processing. These results indicat that working memory is involved more in the processing of low-frequency words. The implications for the teaching of children at the early reading acquisition stage are discussed in this paper.

Characterization Method of Memory Compiler Using Reference Memories (기준 메모리를 이용한 메모리 컴파일러 특성화 방법)

  • Shin, Woocheol;Song, Hyekyoung;Jung, Wonyoung;Cho, Kyeongsoon
    • Journal of the Institute of Electronics and Information Engineers
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    • v.51 no.2
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    • pp.38-45
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    • 2014
  • This paper proposes a characterization method based on the reference memory to characterize memory compiler quickly and accurately. In order to maintain the accuracy of the memory complier and to minimize characterization time, the proposed method models the trends of the generated memories by selecting the reference memories after analyzing the timing trends of the memory compiler. To validate the proposed method, we characterized the 110nm memory compiler derived from 130nm memroy compiler. The average error rate of the characteristics of the memories generated by the proposed method and SPICE simulation is lower than ${\pm}0.1%$. Furthermore, we designed memory BIST test chips at 110nm and 180nm processes and the results of the function test show that the yield is 98.8% and 98.3%, respectively. Therefore, the proposed method is useful to characterize the memory compiler.

Design and demonstrators testing of adaptive airfoils and hingeless wings actuated by shape memory alloy wires

  • Mirone, Giuseppe
    • Smart Structures and Systems
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    • v.3 no.1
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    • pp.89-114
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    • 2007
  • Two aspects of the design of a small-scale smart wing are addressed in this work, related to the ability of the wing to modify its cross section assuming the shape of two different airfoils and to the possibility of deflecting the profiles near the trailing edge in order to obtain hingeless control surfaces. The actuation is provided by one-way shape memory alloy wires eventually coupled to springs, Shape Memory Alloys (SMAs) being among the most promising materials for this kind of applications. The points to be actuated along the profiles and the displacements to be imposed are selecetd so that they satisfactorily approximate the change from an airfoil to the other and to result in an adequate deflection of the control surface; the actuators and their performances are designed so that an adequate wing stiffness is guaranteed, in order to prevent excessive deformations and undesired airfoil shape variations due to aerodynamic loads. The effect of the pressure distributions, calculated by way of the XFOIL software, and of the actuators loads, is estimated by FE analyses of the loaded wing. Two prototypes are then realised incorporating the variable airfoil and the hingeless aileron features respectively, and the verification of their shapes in both the actuated and non-actuated states, supported by image analysis techniques, confirms that interesting results are achievable with the proposed lay out and design considerations.

Experimental analyses of dynamical systems involving shape memory alloys

  • Enemark, Soren;Savi, Marcelo A.;Santos, Ilmar F.
    • Smart Structures and Systems
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    • v.15 no.6
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    • pp.1521-1542
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    • 2015
  • The use of shape memory alloys (SMAs) in dynamical systems has an increasing importance in engineering especially due to their capacity to provide vibration reductions. In this regard, experimental tests are essential in order to show all potentialities of this kind of systems. In this work, SMA springs are incorporated in a dynamical system that consists of a one degree of freedom oscillator connected to a linear spring and a mass, which is also connected to the SMA spring. Two types of springs are investigated defining two distinct systems: a pseudoelastic and a shape memory system. The characterisation of the springs is evaluated by considering differential calorimetry scanning tests and also force-displacement tests at different temperatures. Free and forced vibration experiments are made in order to investigate the dynamical behaviour of the systems. For both systems, it is observed the capability of changing the equilibrium position due to phase transformations leading to hysteretic behaviour, or due to temperature changes which also induce phase transformations and therefore, change in stiffness. Both situations are investigated by promoting temperature changes and also pre-tension of the springs. This article shows several experimental tests that allow one to obtain a general comprehension of the dynamical behaviour of SMA systems. Results show the general thermo-mechanical behaviour of SMA dynamical systems and the obtained conclusions can be applied in distinct situations as in rotor-bearing systems.