• Journal of the Semiconductor & Display Technology
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• v.11 no.2
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• pp.85-91
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• 2012

In this paper, the large data processing and suitable FAT32 file system for industrial system using a PLC and CF memory was implemented. Most of PLC can't save the large data in user data memory. So it's required to the external devices of CF memory or NAND flash memory. The CF memory is used in order to save the large data of PLC system. The file system using the CF memory is NTFS, FAT, and FAT32 system to configure in various ways. Typically, the file system which is widely used in industrial data storage has been implemented as modified FAT32. The conventional FAT 32 file system was not possible for multiple writing and high speed data accessing. The proposed file system was implemented by the large data processing module can be handled that the files are copied at the 40 bytes for 1msec speed logging and creating 8 files at the same time. In a sudden power failure, high reliability was obtained that the problem was solved using a power fail monitor and the non-volatile random-access memory (NVSRAM). The implemented large data processing system was applied the modified file system as FAT32 and the good performance and high reliability was showed.

• Journal of IKEEE
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• v.21 no.4
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• pp.353-357
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• 2017

In order to maintain numerous server systems used in enterprise and data center environments, the most important thing is to prevent the occurrence of UE (Uncorrectable Error) of each server system. With the recent development of cloud services, more memory modules are being used than ever before, while the operating frequency of server systems has increased and the process of developing memory has continued to shrink, making it more likely to fail. In these environments, there is a way to repair memory defects directly in the server system, but there is no currently available guideline to use it effectively. In this paper, we propose a method to effectively prevent memory failure in a server system based on the observation and analysis of memory failure phenomenon in existing system.

• The Journal of the Acoustical Society of Korea
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• v.16 no.2E
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• pp.38-46
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• 1997

The objective of the paper is to compare the computational complexity of five algorithms for computing time-domain second-order Volterra filter outputs in terms of number of real multiplication and addition operations required for implementation. This study shows that if the filter memory length is greater that or equal to 16, the fast algorithm using the overlap-save method and the frequency-domain symmetry properties of the quadratic coefficients is the most efficient among the algorithms investigated in this paper, When the filter memory length is less than 16, the algorithm using the time-domain symmetry properties is better than any other algorithm.

• Nuclear Engineering and Technology
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• v.53 no.2
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• pp.430-438
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• 2021

The spatial distribution of neutron flux or reaction rate was calculated by cell or mesh tally in traditional Monte Carlo simulation. However, either cell or mesh tally leads to the increase of memory consumption and simulation time. In this paper, the function expansion tally (FET) method was developed in Reactor Monte Carlo code RMC to solve this problem. The FET method was applied to the tallies of neutron flux distributions of uranium block and PWR fuel rod models. Legendre polynomials were used in the axial direction, while Zernike polynomials were used in the radial direction. The results of flux, calculation time and memory consumption of different expansion orders were investigated, and compared with the mesh tally. Results showed that the continuous distribution of flux can be obtained by FET method. The flux distributions were consistent with that of mesh tally, while the memory consumption and simulation time can be effectively reduced. Finally, the convergence analysis of coefficients of polynomials were performed, and the selection strategy of FET order was proposed based on the statistics uncertainty of the coefficients. The proposed method can help to determine the order of FET, which was meaningful for the efficiency and accuracy of FET method.

• Proceedings of the KIEE Conference
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• 2005.05a
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• pp.191-193
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• 2005

Flash memories are one of best media to support portable computer's storages. However, we need to improve traditional data management scheme due to the relatively slow characteristics of flash operation as compared to RAM memory. In order to achieve this goal, we devise a new scheme called Flash Two Phase Locking (F2PL) scheme for efficient data processing. F2PL improves transaction performance by allowing multi version reads and efficiently handling slow flash write/erase operation in lock management process.

• 전기의세계
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• v.22 no.2
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• pp.45-50
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• 1973

Amorphous semiconducting diodes from As Te Ge systm of which resitivity are 10$^{6}$ -10$^{8}$ .ohm.-cm order, are made and they exhibited several conducting states. A high conductivity, low conductivity and memory state are reported. Temperature dependency of the specimens are widerange. According to the procedure and cooling method, specimens are made easily or not. Threshold voltage of switching and memory diodes is in proportional to compositonal quantity of Arsenic. Threshold voltage is changed widely according to ambient temperature. Threshold voltage of #132 is 620V at 25.deg. C, 70V at 100.deg. C.

• Journal of KIISE:Software and Applications
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• v.37 no.11
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• pp.851-858
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• 2010

Most mobile devices use a NAND flash memory as their secondary memory. A compressed code of the firmware is stored in the NAND flash memory of mobile devices in order to reduce the size and the loading time of the firmware from the NAND flash memory to a main memory. In order to use a demand paging properly, a compressed code should be decompressed very quickly. The thesis introduces a new dictionary based compression algorithm for the fast decompression. The introduced compression algorithm uses a different method with the current LZ method by storing the "exclusive or" value of the two instructions when the instruction for compression is not equal to the referenced instruction. Therefore, the thesis introduces a new compression format that minimizes the bit operation in order to improve the speed of decompression. The experimental results show that the decoding time is reduced up to 5 times and the compression ratio is improved up to 4% compared to the zlib. Moreover, the proposed compression method with the fast decoding time leads to 10-20% speed up of booting time compared to the booting time of the uncompressed method.

• Journal of Broadcast Engineering
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• v.23 no.5
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• pp.606-613
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• 2018

This study is concerned with implementing an external memory expansion device for large-scale image processing. It consists of an external memory adapter card with a PCI(Peripheral Component Interconnect) Express Gen3 x8 interface mounted on a graphics workstation for image processing and an external memory board with external DDR(Dual Data Rate) memory. The connection between the memory adapter card and the external memory board is made through the optical interface. In order to access the external memory, both Programmable I/O and DMA(Direct Memory Access) methods can be used to efficiently transmit and receive image data. We implemented the result of this study using the boards equipped with Altera Stratix V FPGA(Field Programmable Gate Array) and 40G optical transceiver and the test result shows 1.6GB/s bandwidth performance.. It can handle one channel of 4K UHD(Ultra High Density) image. We will continue our study in the future for showing bandwidth of 3GB/s or more.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.31-32
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• 2010

In our previous reports [1-3], electron transport for the switching and memory devices using alkyl thiol-tethered Ru-terpyridine complex compounds with metal-insulator-metal crossbar structure has been presented. On the other hand, among organic memory devices, a memory based on the OFET is attractive because of its nondestructive readout and single transistor applications. Several attempts at nonvolatile organic memories involve electrets, which are chargeable dielectrics. However, these devices still do not sufficiently satisfy the criteria demanded in order to compete with other types of memory devices, and the electrets are generally limited to polymer materials. Until now, there is no report on nonvolatile organic electrets using nano-interfaced organic monomer layer as a dielectric material even though the use of organic monomer materials become important for the development of molecularly interfaced memory and logic elements. Furthermore, to increase a retention time for the nonvolatile organic memory device as well as to understand an intrinsic memory property, a molecular design of the organic materials is also getting important issue. In this presentation, we report on the OFET memory device built on a silicon wafer and based on films of pentacene and a SiO2 gate insulator that are separated by organic molecules which act as a gate dielectric. We proposed push-pull organic molecules (PPOM) containing triarylamine asan electron donating group (EDG), thiophene as a spacer, and malononitrile as an electron withdrawing group (EWG). The PPOM were designed to control charge transport by differences of the dihedral angles induced by a steric hindrance effect of side chainswithin the molecules. Therefore, we expect that these PPOM with potential energy barrier can save the charges which are transported to the nano-interface between the semiconductor and organic molecules used as the dielectrics. Finally, we also expect that the charges can be contributed to the memory capacity of the memory OFET device.[4]

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.9
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• pp.457-464
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• 2005

In this paper a 3D memory system that allows 17 access types at an arbitrary position is introduced. The proposed memory system is based on two main functions: memory module assignment function and address assignment function. Based on them, the memory system supports 17 access types: 13 Lines, 3 Rectangles, and 1 Hexahedron. That is, the memory system allows simultaneous access to multiple data in any access types at an arbitrary position with a constant interval. In order to allow 17 access types the memory system consists of memory module selection circuitry, data routing circuitry for READ/WRITE, and address calculation/routing circuitry In the point of view of a developer and a programmer, the memory system proposed in this paper supports easy hardware extension according to the applications and both of them to deal with it as a logical three-dimensional away In addition, multiple data in various across types can be simultaneously accessed with a constant interval. Therefore, the memory system is suitable for building systems related to ,3D applications (e.g. volume rendering and volume clipping) and a frame buffer for multi-resolution.