• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1991년도 한국자동제어학술회의논문집(국제학술편); KOEX, Seoul; 22-24 Oct. 1991
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• pp.1817-1822
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• 1991

A method of reducing overhead caused by the processor synchronization process and common memory accesses in finely grained tasks is described. We propose a scheduler which considers the preparation time during searching to minimize the redundant accesses to shared memory. Since the suggested hardware (synchronizer) determines the access order of processors and bus arbitration simultaneously by including the synchronization process into the bus arbitration process, the synchronization time vanishes. Therefore this synchronizer has no overhead caused by the processor synchronization[l]. The proposed scheduler algorithm is processed in parallel. The processes share the upper bound derived by each searching and the lower bound function is built considering the preparation time in order to eliminate as many searches as possible. An application of the proposed method to a multi-DSP system to calculate inverse dynamics for robot arms, showed that the sampling time can be twice shorter than that of the conventional one.

• Journal of the Korean Institute of Telematics and Electronics S
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• 제35S권2호
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• pp.97-105
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• 1998

Subband/DCT coding has been introduced in order to transmit images of various resultions using one given image-codec, for nowadays there are various grades of quality in visual communication services. However, subband/DCT results in the increawse of multiplication number and memory size. In order to resolve this problem, we propose block-based subband/DCT coding in this paper. In block-based subband/DCT, the number of multiplications is not only reduced because we combine subband decomposistion with DCT, but the size of memory is also reduced because images can be parallel-processed block by block. We show that the number of multiplications is reduced, by analyzing the property ofblock-based subband/DCT matrix mathematically, and examine the performance of proposed coder, which adopts JPEG as backhand-coder after block-based subband/DCT.

• Journal of the Korean Institute of Telematics and Electronics A
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• 제29A권8호
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• pp.99-109
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• 1992

First, the coupling faults of semiconductor memory are classified in detail. The chained coupling fault is introduced and defined, which results from sequential influencing of the coupling effects among memory cells, and its mapping relation is described. The linked coupling fault and its order are defined. Second, the deterministic “Algorithm GA” is proposed, which detects stuack-at faults, transition faults, address decoder faults, unlinked 2-coupling faults, and unlinked chained coupling faults. The time complexity and the fault coverage are improved in this algorithm. Third, it is proved that the march test of an address sequence can detect 97.796% of the linked 2-coupling faults with order 2. The deterministic “Algorithm NA” proposed can detect to the limit. The time complexity and the fault coverage are improved in this algorithm.

• Smart Structures and Systems
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• 제5권6호
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• pp.645-662
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• 2009

Adaptive wings are capable of properly modifying their shape depending on the current aerodynamic conditions, in order to improve the overall performance of a flying vehicle. In this paper is presented the concept design of a small-scale compliant wing rib whose outline may be distorted in order to switch from an aerodynamic profile to another. The distortion loads are induced by shape memory alloy actuators placed within the frame of a wing section whose elastic response is predicted by the matrix method with beam formulation. Genetic optimization is used to find a wing rib structure (corresponding to the first airfoil) able to properly deforms itself when loaded by the SMA-induced forces, becoming as close as possible to the desired target shape (second airfoil). An experimental validation of the design procedure is also carried out with reference to a simplified structure layout.

• Structural Engineering and Mechanics
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• 제60권3호
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• pp.507-527
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• 2016

The use of shape memory alloys (SMAs) has been seriously considered in seismic engineering due to their capabilities, such as the ability to tolerate cyclic deformations and dissipate energy. Five 3-D extended end-plate connection models have been created, including one conventional connection and four connections with Nitinol bolts of four different prestress forces. Their cyclic behaviors have been investigated using the finite element method software ANSYS. Subsequently, the moment-rotation responses of the connections have been derived by subjecting them to cyclic loading based on SAC protocol. The results obtained in this research indicate that the conventional connections show residual deformations despite their high ductility and very good energy dissipation; therefore, they cannot be repaired after loading. However, while having good energy dissipation and high ductility, the connections equipped with Nitinol bolts have good recentering capability. Moreover, a connection with the mentioned specifications has been modeled, except that only the external bolts replaced with SMA bolts and assessed for seismic loading. The suggested connection shows high ductility, medium energy dissipation and very good recentering. The main objective of this research is to concentrate the deformations caused by cyclic loading on the connection in order to form super-elastic hinge in the connection by the deformations of the shape memory alloy bolts.

• Journal of the Korea Society of Computer and Information
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• 제22권2호
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• pp.1-7
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• 2017

Recently, NAND flash memory, which is used as a storage medium, is replacing HDD (Hard Disk Drive) at a high speed due to various advantages such as fast access speed, low power, and easy portability. In order to apply NAND flash memory to a computer system, a Flash Translation Layer (FTL) is indispensably required. FTL provides a number of features such as address mapping, garbage collection, wear leveling, and hot data identification. In particular, hot data identification is an algorithm that identifies specific pages where data updates frequently occur. Hot data identification helps to improve overall performance by identifying and managing hot data separately. MHF (Multi hash framework) technique, known as hot data identification technique, records the number of write operations in memory. The recorded value is evaluated and judged as hot data. However, the method of counting the number of times in a write request is not enough to judge a page as a hot data page. In this paper, we propose hot data identification which considers not only the number of write requests but also the persistence of write requests.

• The Transactions of the Korean Institute of Electrical Engineers A
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• 제48권12호
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• pp.1554-1563
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• 1999

This paper presents the design of high speed processor for a sequence logic control using field programmable gate array(FPGA). The sequence logic controller is widely used for automating a variety of industrial plants. The FPGA designed by VHDL consists of program and data memory interface block, input and output block, instruction fetch and decoder block, register and ALU block, program counter block, debug control block respectively. Dedicated clock inputs in the FPGA were used for high speed execution, and also the program memory was separated from the data memory for high speed execution of the sequence instructions at 40 MHz clock. Therefore it was possible that sequence instructions could be operated at the same time during the instruction fetch cycle. In order to reduce the instruction decoding time and the interface time of the data memory interface, an instruction code size was implemented by 16 bits or 32 bits respectively. And the real time debug operation was implemented for easy debugging the designed processor. This FPGA was synthesized by pASIC 2 SpDE and Synplify-Lite synthesis tool of Quick Logic company. The final simulation for worst cases was successfully performed under a Verilog HDL simulation environment. And the FPGA programmed for an 84 pin PLCC package was applied to sequence control system with inputs and outputs of 256 points. The designed processor for the sequence logic was compared with the control system using the DSP(TM320C32-40MHz) and conventional PLC system. The designed processor for the sequence logic showed good performance.

• The Journal of Internal Korean Medicine
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• 제27권1호
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• pp.253-264
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• 2006

Object: This research investigated effects of Jujadokseo-hwan on mice with Alzheimer's Disease induced by $amyloid-{\beta}$. According to Dongyibogam, Jujadokseo-hwan can cure amnesia. Amyloid-B is believed to induce oxidative stress and inflammation in the brain, postulated to play important roles in the pathogenesis of Alzheimer's disease. In this way $Amyloid-{\beta}$ induces Alzheimer's Disease. Methods : In order to make an efficient prescription and cope with dementia, learning and memory functions of mice were tested on passive avoidance test and V-maze task. $NF-{\kappa}B$ were measured from protein derived from the brain. RT-PCR was done for !gene analysis. Primers were protein kinase Band $NGF-{\alpha}$. Results : 1. Jujadokseo-hwan was effective for memory capacity on passive avoidance test. but noneffective for spatial memory capacity and locomotor activity on Y -maze task. 2. The measurement of $NF-{\kappa}B$ showed upward tendancies and the result of RT-PCR showed up-regulation when given Jujadokseo-hwan by mouth. Conclusion: Results suggest that Jujadokseo-hwan is effective on mice with Alzheimer's Disease induced by $amyloid-{\beta}$.

• The KIPS Transactions:PartA
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• 제11A권7호
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• pp.475-482
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• 2004

We live in the flood of information due to advancement of information communication and increase of E-mail. Managing users huge in-formation systematically and speedy searching are needed in these social advancement. In this thesis, in order to satisfy these requirement, We suggested Real-time LDAP Interface using Main Memory Resident Database Management System which can manage a lot of information fast systematically. It is expected that system can provide advantage of performance improvement through replacing Main Memory Resident Database Management System without change of application which is required high speed process.

• Journal of Internet Computing and Services
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• 제6권1호
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• pp.73-84
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• 2005

ALTIBASE/sup TM/ is the relational main-memory DBMS in which a main memory is primarily used as the main storage device. We present the database replication strategies and techniques of the ALTIBASETM system in order to meet the requirement of high availability and efficient transaction processing. Our process architecture for replication management and its communication model are proposed, and database replication protocols are also described. We show the experimental result of transaction processing rate with various DBMS parameters and overall performance of database replication system as compared to standalone system.