• Title/Summary/Keyword: Order memory

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Fabrication Process and Reliability Evaluation of Shape Memory Alloy Composite (형상기억복합재료의 저조공정 및 신뢰성 평가)

  • Lee, Jin-Kyung;Park, Young-Chul;Lee, Kyu-Chang;Choi, Il-Kook;Lee, Joon-Hyun
    • Journal of the Korean Society for Nondestructive Testing
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    • v.21 no.6
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    • pp.634-641
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    • 2001
  • Shape memory alloy has been used to improve the tensile strength of composite by the occurrence of compressive residual stress in matrix using its shape memory effect. In order to fabricate shape memory alloy composite, TiNi alloy and A16061 were used as reinforcing material and mix, respectively. In this study, TiNi/A16061 shape memory alloy composite was made by using hot press method. However, the specimen fabricated by this method had the bonding problem at the boundary between TiNi fiber and Al matrix when the load was applied to it. A cold rolling was imposed to the specimen to improve the bonding effect. It was found that tensile strength of specimen subjected to cold rolling was more increased than that of specimen which did not underwent cold rolling. In addition, acoustic emission technique was used to quantify the microscopic damage behavior of cold rolled TiNi/A16061 shape memory alloy composite at high temperature.

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A Subthreshold Slope and Low-frequency Noise Characteristics in Charge Trap Flash Memories with Gate-All-Around and Planar Structure

  • Lee, Myoung-Sun;Joe, Sung-Min;Yun, Jang-Gn;Shin, Hyung-Cheol;Park, Byung-Gook;Park, Sang-Sik;Lee, Jong-Ho
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.12 no.3
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    • pp.360-369
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    • 2012
  • The causes of showing different subthreshold slopes (SS) in programmed and erased states for two different charge trap flash (CTF) memory devices, SONOS type flash memory with gate-all-around (GAA) structure and TANOS type NAND flash memory with planar structure were investigated. To analyze the difference in SSs, TCAD simulation and low-frequency noise (LFN) measurement were fulfilled. The device simulation was performed to compare SSs considering the gate electric field effect to the channel and to check the localized trapped charge distribution effect in nitride layer while the comparison of noise power spectrum was carried out to inspect the generation of interface traps ($N_{IT}$). When each cell in the measured two memory devices is erased, the normalized LFN power is increased by one order of magnitude, which is attributed to the generation of $N_{IT}$ originated by the movement of hydrogen species ($h^*$) from the interface. As a result, the SS is degraded for the GAA SONOS memory device when erased where the $N_{IT}$ generation is a prominent factor. However, the TANOS memory cell is relatively immune to the SS degradation effect induced by the generated $N_{IT}$.

An Analysis of Memory Access Complexity for HEVC Decoder (HEVC 복호화기의 메모리 접근 복잡도 분석)

  • Jo, Song Hyun;Kim, Youngnam;Song, Yong Ho
    • Journal of the Institute of Electronics and Information Engineers
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    • v.51 no.5
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    • pp.114-124
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    • 2014
  • HEVC is a state-of-the-art video coding standard developed by JCT-VC. HEVC provides about 2 times higher subjective coding efficiency than H.264/AVC. One of the main goal of HEVC development is to efficiently coding UHD resolution video so that HEVC is expected to be widely used for coding UHD resolution video. Decoding such high resolution video generates a large number of memory accesses, so a decoding system needs high-bandwidth for memory system and/or internal communication architecture. In order to determine such requirements, this paper presents an analysis of the memory access complexity for HEVC decoder. we first estimate the amount of memory access performed by software HEVC decoder on an embedded system and a desktop computer. Then, we present the memory bandwidth models for HEVC decoder by analyzing the data flow of HEVC decoding tools. Experimental results show the software decoder produce 6.9-40.5 GB/s of DRAM accesses. also, the analysis reveals the hardware decoder requires 2.4 GB/s of DRAM bandwidth.

Design and Performance Evaluation of Receiver Feedback Closed Loop Pre-Distortion System (수신기 포함 폐루프 전치왜곡기 설계와 성능 평가)

  • Bok, Junyeong;Jo, Byung Gak;Baek, Gwang Hoon;Ryu, Heung-Gyoon
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.37A no.10
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    • pp.827-833
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    • 2012
  • The receiver performance is degraded by nonlinear memory problem in communication system. The pre-distorter techniques are an effective technique to compensate for the nonlinear distortion of the HPA without memory effects. However, memory effect of HPA can no longer be ignored when data signal is transmitted in high speed. Many adaptive pre-distorter schemes have been studied to compensate for memory effect problem of HPA in transmitter. The complexity and cost of satellite will increase when using adaptive pre-distorter in satellite communication system. In this paper, we propose receiver feedback closed loop pre-distortion technique in order to compensate for nonlinear problem of HPA with memory problem. The purpose of this paper is to reduce complexity and cost of satellite design by using only pre-distorter at terrestrial station.

Design of Shared Memory Controller Device Driver in Embedded System (임베디드 시스템에서의 공유 메모리 컨트롤러 디바이스 드라이버 설계)

  • Moon, Ji-Hoon;Oh, Jae-Chul
    • The Journal of the Korea institute of electronic communication sciences
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    • v.9 no.6
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    • pp.703-709
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    • 2014
  • In the AMP(Asymmetric Multiprocessing) based dual core using core-specific operating system in a single processor system, shared memory method is used to send data between processors in dual core. To used shared memory in different operating systems, there is a problem of needing to solving the issue of message communication and synchronization between the two operations systems. In this paper, separate memory controller was used for data sharing between different processor cores in dual core environment. This controller can designate two slave ports to allow simultaneous access from two processors, and in the case of process data simultaneously by two processors, priority order of slave ports is determined through memory mediator. When sending data from A to B processor, SRAM area was logically separated into 8 pages. It allowed using memory area from multiple processes with the size of 4KByte per page, and control register with the size of 4Byte was used to discern the usability of current page.

Comparison of Working Memory Among the Subtypes of Child and Adolescent Attention-Deficit/Hyperactivity Disorder (아동.청소년주의력결핍/과잉행동장애 하위유형에 따른 작업기억의 비교)

  • Lee, Soyoung Irene;Lim, Eun-Ji;Park, Joon-Ho;Jung, Han-Yong
    • Korean Journal of Biological Psychiatry
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    • v.17 no.2
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    • pp.70-78
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    • 2010
  • Objectives : This study investigated the differences of working memory among the subtypes of ADHD. Methods : Eighty-one children and adolescents with ADHD and thirty normal controls were recruited. Children with any cognitive disorders and low intelligence were excluded. In order to evaluate the verbal and visuospatial working memory, Digit span and Finger windows tasks were measured, respectively. Performances on these measures between children with ADHD and controls were compared. Further, performances among the groups of ADHD predominantly inattentive(ADHD-IA)(n=40), predominantly hyperactive-impulsive(ADHD-HI)(n= 10), and combined type(ADHD-C)(n=31), were compared. Results : Scores of Finger windows forward task were lower in the ADHD group as compared to the control group, whereas, the Digit span forward showed no difference. Both scores of Digit span backward and Finger windows backward task were lower in the ADHD group than the controls. Children with ADHD-IA performed poorer than children with ADHD-C on the Finger windows backward task. Conclusion : The results of this study showed that children with ADHD have deficits in spatial short-term memory and verbal and visuospatial working memory when compared to normal children. The deficits were evident in children with ADHD-IA subtype and in particular, performance on the visuospatial working memory task in this group was poorer than the ADHD-C group.

Time-domain 3D Wave Propagation Modeling and Memory Management Using Graphics Processing Units (그래픽 프로세서를 이용한 시간 영역 3차원 파동 전파 모델링과 메모리 관리)

  • Kim, Ahreum;Ryu, Donghyun;Ha, Wansoo
    • Geophysics and Geophysical Exploration
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    • v.19 no.3
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    • pp.145-152
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    • 2016
  • We used graphics processing units for an efficient time-domain 3D wave propagation modeling. Since graphics processing units are designed for massively parallel processes, we need to optimize the calculation and memory management to fully exploit graphics processing units. We focused on the memory management and examined the performance of programs with respect to the memory management methods. We also tested the effects of memory transfer on the performance of the program by varying the order of finite difference equation and the size of velocity models. The results show that the memory transfer takes a larger portion of the running time than that of the finite difference calculation in programs transferring whole 3D wavefield.

Memory Reduction Method of Radix-22 MDF IFFT for OFDM Communication Systems (OFDM 통신시스템을 위한 radix-22 MDF IFFT의 메모리 감소 기법)

  • Cho, Kyung-Ju
    • The Journal of Korea Institute of Information, Electronics, and Communication Technology
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    • v.13 no.1
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    • pp.42-47
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    • 2020
  • In OFDM-based very high-speed communication systems, FFT/IFFT processor should have several properties of low-area and low-power consumption as well as high throughput and low processing latency. Thus, radix-2k MDF (multipath delay feedback) architectures by adopting pipeline and parallel processing are suitable. In MDF architecture, the feedback memory which increases in proportion to the input signal word-length has a large area and power consumption. This paper presents a feedback memory size reduction method of radix-22 MDF IFFT processor for OFDM applications. The proposed method focuses on reducing the feedback memory size in the first two stages of MDF architectures since the first two stages occupy about 75% of the total feedback memory. In OFDM transmissions, IFFT input signals are composed of modulated data and pilot, null signals. In order to reduce the IFFT input word-length, the integer mapping which generates mapped data composed of two signed integer corresponding to modulated data and pilot/null signals is proposed. By simulation, it is shown that the proposed method has achieved a feedback memory reduction up to 39% compared to conventional approach.

An Efficient Cache Management Scheme for Load Balancing in Distributed Environments with Different Memory Sizes (상이한 메모리 크기를 가지는 분산 환경에서 부하 분산을 위한 캐시 관리 기법)

  • Choi, Kitae;Yoon, Sangwon;Park, Jaeyeol;Lim, Jongtae;Lee, Seokhee;Bok, Kyoungsoo;Yoo, Jaesoo
    • KIISE Transactions on Computing Practices
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    • v.21 no.8
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    • pp.543-548
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    • 2015
  • Recently, volume of data has been growing dramatically along with the growth of social media and digital devices. However, the existing disk-based distributed file systems have limits to their performance of data processing or data access, due to I/O processing costs and bottlenecks. To solve this problem, the caching technique is being used to manage data in the memory. In this paper, we propose a cache management scheme to handle load balancing in a distributed memory environment. The proposed scheme distributes the data according to the memory size, n distributed environments with different memory sizes. If overloaded nodes occur, it redistributes the the access time of the caching data. In order to show the superiority of the proposed scheme, we compare it with an existing distributed cache management scheme through performance evaluation.

Design of Advanced PCM Encoder Architecture for Efficient Channel Information Memory Management (효율적인 채널 정보 메모리 관리를 위한 PCM 엔코더 설계)

  • Ro, Yun-Hee;Kim, Geon-Hee;Kim, Dong-Young;Kim, Bok-Ki;Lee, Nam-Sik
    • Journal of Advanced Navigation Technology
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    • v.24 no.4
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    • pp.305-313
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    • 2020
  • Telemetry system is a system that transmits status information data acquired from the aircraft to the ground station. PCM encoder needs memory to store channel information in order to generate a frame format using the acquired data. Generally, telemetry systems in large aircraft require much larger memory for the increased acquisition channel information due to the increased sensors and subsystems. However, they have difficulty to store all channel information in limited memory. In this paper, we suggests and implements an advanced PCM encoder that can efficiently manage memory by minimizing duplicated channel information. This novel PCM encoder allocates duplicated channel information to memory only once. And, sub commutation channels having different information for each minor frame are allocated to the memory by multiples of sub commutation channels. Finally, the suggested PCM encoder was proved by simulation that composed channels of various measurement cycles.