• Journal of information and communication convergence engineering
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• v.14 no.1
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• pp.26-34
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• 2016

The alignment of DNA sequences is one of the important processes in the field of bioinformatics. The Smith-Waterman algorithm (SWA) performs optimally for aligning sequences but is computationally expensive. Field programmable gate array (FPGA) performs the best on parameters such as cost, speed-up, and ease of re-configurability to implement SWA. The performance of FPGA-based SWA is dependent on efficient cell-basic implementation-unit design. In this paper, we present an optimized systolic cell design while avoiding oversimplification, very large-scale integration (VLSI)-level design, and direct mapping of iterative equations such as previous cell designs. The proposed design makes efficient use of hardware resources and provides portability as the proposed design is not based on gate-level details. Our cell design implementing a linear gap penalty resulted in a performance improvement of 32× over a GPP platform and surpassed the hardware utilization of another implementation by a factor of 4.23.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.263-266
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• 2012

This paper describes an efficient hardware implementation of Whirlpool hash function as ISO/IEC 10118-3 standard. Optimized timing is achieved by using pipelined small LUTs, and Whirlpool block cipher and key schedule have been implemented in parallel for improving throughput. In key schedule, key addition is area-optimized by using inverters and muxes instead of using rom and xor gates. This hardware has been implemented on Virtex5-XC5VSX50T FPGA device. Its maximum operating frequency is about 151MHz, and throughput is about 950Mbps.

• Journal of Convergence for Information Technology
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• v.11 no.4
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• pp.19-25
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• 2021

This study proposes a digital twin implementation method through simulation so that the manufacturing process can be optimized in a manual manufacturing site. The scope of the proposal is a knowledge management mechanism that collects manual motion with a sensor and optimizes the manufacturing process with repetitive experimental data for motion recognition. In order to achieve the research purpose, a simulation of the distribution site was conducted, and a plan to create an optimized digital twin was prepared by repeatedly experiencing the work simulation based on the basic knowledge expressed by the worker's experience. As a result of the experiment, it was found that it is possible to continuously improve the manufacturing process by transmitting the result of configuring the optimized resources to the physical system by generating the characteristics of the work space configuration and working step within a faster time with the simulation that creates the digital twin.

• Asia pacific journal of information systems
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• v.7 no.1
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• pp.7-24
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• 1997

Executive information system (EIS) is a computer-based information system that supports decision makings ana management activities for senior executives. Data warehouse is a database that receives data copies from legacy systems and external data sources. Data warehouse is typically optimized for decision supports and can be an attractive solution for EIS implementation. This paper proposes an architecture for implementing EIS by the use of data warehouse. The architecture consists of ten implementation layers. Interrelationships among these layers are investigated for an effective EIS implementation. An EIS prototype for a real-fife enterprise is implemented to demonstrate the usefulness of the proposed architecture.

• Proceedings of the Korean Operations and Management Science Society Conference
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• 1996.10a
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• pp.254-257
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• 1996

Executive information system (EIS) is a computer-based information system that supports decision makings and management activities for senior executives. Data warehouse is a database that receives data copies from legacy systems and external data sources. Data warehouse is typically optimized for decision supports and can be an attractive solution for EIS implementation. This paper proposes an architecture for implementing EIS by the use of data warehouse. The architecture consists of ten implementation layers. Interrelationships among these layers are investigated for an effective EIS implementation. An EIS prototype for a real-life enterprise is implemented to demonstrate the usefulness of the proposed architecture.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.560-563
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• 1999

In this paper, we present an optimal hardware implementation for preprocessing of a person identification algorithm utilizing vein pattern of dorsal surface of hand. For the vein pattern recognition, the computational burden of the algorithm lies mainly in the preprocessing of the input images, especially in lowpass filtering. we could reduce the identification time to one tenth by hardware design of the lowpass filter compared to sequential computations. In terms of the computation accuracy, the simulation results show that the CSD code provided an optimized coefficient value with about 91.62% accuracy in comparison with the floating point implementation of current coefficient value of the lowpass filter. The post-simulation of a VHDL model has been performed by using the ModelSim$^{TM}$. The implemented chip operates at 20MHz and has the operational speed of 55.107㎳.㎳.

• ETRI Journal
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• v.37 no.4
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• pp.667-676
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• 2015

The third-party FFT IP cores available in today's markets do not provide the desired speed demands for optical communication. This study deals with the design and implementation of a 256-point Radix-4 100 Gbit/s FFT, where computational steps are reconsidered and optimized for high-speed applications, such as radar and fiber optics. Alternative methods for FFT implementation are investigated and Radix-4 is decided to be the optimal solution for our fully parallel FPGA application. The algorithms that we will implement during the development phase are to be tested on a Xilinx Virtex-6 FPGA platform. The proposed FFT core has a fully parallel architecture with a latency of nine clocks, and the target clock rate is 312.5 MHz.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.3
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• pp.387-393
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• 1987

The introduction of a digiral subscriber loop transmission system necessitates an optimized line interface solution. To meet this objective an adaptive line equalizer has been developed. The equalizer can be compensated up to 42 dB line loss at 200KHz, and operated up to 3.2 Km transmission length (0.4 mm\ulcornercable)at a rate of 400Kb/s. This has been builted using a variable \ulcorner equalizer to compensate a frequency-attenuation characteristics of metallic cable, an AGC (automatic gain control) circuits with simple control algorithm, and various filters to minimize a transmission constraints over subscriber loop. The purpose of this paper is to present a short description of a design of the adaptive line equalizer with a summary of implementation results. Some design concepts and considerations which results in an implementation of the equalizer are also given.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.11 no.7
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• pp.3543-3557
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• 2017

Compression is a very important technique for remotely sensed hyperspectral images. The lossless compression based on the recursive least square (RLS), which eliminates hyperspectral images' redundancy using both spatial and spectral correlations, is an extremely powerful tool for this purpose, but the relatively high computational complexity limits its application to time-critical scenarios. In order to improve the computational efficiency of the algorithm, we optimize its serial version and develop a new parallel implementation on graphics processing units (GPUs). Namely, an optimized recursive least square based on optimal number of prediction bands is introduced firstly. Then we use this approach as a case study to illustrate the advantages and potential challenges of applying GPU parallel optimization principles to the considered problem. The proposed parallel method properly exploits the low-level architecture of GPUs and has been carried out using the compute unified device architecture (CUDA). The GPU parallel implementation is compared with the serial implementation on CPU. Experimental results indicate remarkable acceleration factors and real-time performance, while retaining exactly the same bit rate with regard to the serial version of the compressor.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.7
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• pp.1510-1516
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• 2011

As emergence of the ubiquitous society, it is possible to access the network for services needed to us in anytime and anywhere. The phenomena has been accelerated by revitalization of the sensor network offering the sensing information and data. Currently, sensor network contributes the convenience for various services such as environment monitoring, health care and home automation. However, sensor network has a weak point compared to traditional network, which is easily exposed to attacker. For this reason, messages communicated over the sensor network, are encrypted with symmetric key and transmitted. A number of symmetric cryptography algorithms have been researched. Among of them HIGHT algorithm in hardware and software implementation are more efficient than tradition AES in terms of speed and chip size. Therefore, it is suitable to resource constrained devices including RFID tag, Sensor node and Smart card. In the paper, we present the optimized software implementation on the ultra-light symmetric cryptography algorithm, HIGHT.