• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.7
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• pp.1303-1310
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• 2016

In this paper, electrocardiogram (ECG) analog front end with supply voltage of 0.5V has been designed and verified by measurements of fabricated chip. ECG is composed of instrument amplifier, 6th order gm-C low pass filter and variable gain amplifier. The instrument amplifier is designed to have gain of 34.8dB and the 6th order gm-C low pass filter is designed to obtain the cutoff frequency of 400Hz. The operational transconductance amplifier of the low pass filter utilizes body-driven differential input stage for low voltage operation. The variable gain amplifier is designed to have gain of 6.1~26.4dB. The electrocardiogram analog front end are fabricated in TSMC $0.18{\mu}m$ CMOS process with chip size of $858{\mu}m{\times}580{\mu}m$. Measurements of the fabricated chip is done not to saturate the gain of ECG by changing the external resistor and measured gain of 28.7dB and cutoff frequency of 0.5 - 630Hz are obtained using the supply voltage of 0.5V.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.2
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• pp.214-219
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• 2011

This paper presents a multi-band low noise amplifier(LNA) with switching operation for 2.4, 3.5 and 5.2 GHz bands using CMOS 0.18 um technology. The proposed circuit uses switching transistors to achieve the input and output matching for multi-band. By using the switching transistors, we can adjust the transconductance, gate inductance and gatesource capacitance at input stage and total output capacitance at output stage. The proposed LNA exhibits gain of 14.2, 12 and 11 dB and noise figure(NF) of 3, 2.9 and 2.8 dB for 2.4, 3.5 and 5.2 GHz, respectively.

• Journal of IKEEE
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• v.14 no.4
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• pp.257-262
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• 2010

We design a CMOS front-end with wide variable gain and low power consumption for 5.25 GHz band. To obtain wide variable gain range, a p-type metal-oxide-semiconductor field-effect transistor (PMOS FET) in the low noise amplifier (LNA) section is connected in parallel. For a mixer, single balanced and folded structure is employed for low power consumption. Using this structure, the bias currents of the transconductance and switching stages in the mixer can be separated without using current bleeding path. The proposed front-end has a maximum gain of 33.2 dB with a variable gain range of 17 dB. The noise figure and third-order input intercept point (IIP3) are 4.8 dB and -8.5 dBm, respectively. For this operation, the proposed front-end consumes 7.1 mW at high gain mode, and 2.6 mW at low gain mode. The simulation results are performed using Cadence RF spectre with the Taiwan Semiconductor Manufacturing Company (TSMC) $0.18\;{\mu}m$ CMOS technology.)